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December 2022 - Volume 18 Issue 3 (4)

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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

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November 2018 - Volume 14 Issue 3 (3)

October 2012 - Volume 8 Issue 3 (3)

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December 2019 - Volume 15 Issue 3 (2)

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July 2023 - Volume 19 Issue 2 (2)

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March 2015 - Volume 11 Issue 1 (2)

Memory Debug (2)

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December 2017 - Volume 13 Issue 3 (1)

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Show Less

January 2023

Functional Verification: Badging and Certification
UVM - Universal Verification Methodology Jan 01, 2023 Siemens Learning Center link

December 2022

Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Dec 26, 2022 Harry Foster link
Part 8: IC/ASIC Resource Trends
Planning, Measurement and Analysis Dec 18, 2022 Harry Foster link
Part 9: ASIC Verification Technology Adoption Trends
Planning, Measurement and Analysis Dec 18, 2022 Harry Foster link
Harry Foster - Siemens EDA
Formal Verification Dec 08, 2022 Harry Foster mp4
Holger Busch - Infineon
Formal Verification Dec 08, 2022 Holger Busch - Infineon mp4
Katharina Ceesay-Seitz - ETH Zurich
Formal Verification Dec 08, 2022 Katharina Ceesay-Seitz mp4
Philippe Luc - Codasip
Formal Verification Dec 08, 2022 Philippe Luc - Codasip mp4
Saranyu Chattopadhyay - Stanford University
Formal Verification Dec 08, 2022 Saranyu Chattopadhyay mp4
Out of the Verification Crisis - Improving RTL Quality
Planning, Measurement and Analysis Dec 01, 2022 Harry Foster Article
Effective Resource Utilization in PCIe® Gen6: Shared Flow Control
Verification IP Dec 01, 2022 Vidushi Goel - Siemens Eda Article
Data Integrity through TLP Encryption in PCI Express®
Verification IP Dec 01, 2022 Om Prakash - Siemens Eda Article
Missing Your Buttons and Menus? Create Your Own
Debug Dec 01, 2022 Vishal Baskar Article

November 2022

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Nov 28, 2022 Harry Foster link
Part 6: FPGA Language and Library Trends
Planning, Measurement and Analysis Nov 21, 2022 Harry Foster link
Functional Verification Study - 2022
Planning, Measurement and Analysis Nov 16, 2022 Harry Foster Webinar
Part 5: FPGA Verification Technology Adoption Trends
Planning, Measurement and Analysis Nov 13, 2022 Harry Foster link
Part 4: FPGA Verification Effort Trends (Continued)
Planning, Measurement and Analysis Nov 06, 2022 Harry Foster link
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai Webinar
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai pdf

October 2022

Part 3: FPGA Verification Effort Trends
Planning, Measurement and Analysis Oct 30, 2022 Harry Foster link
CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma pdf
CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma Webinar
Formal and the Next Normal
Formal Verification Oct 19, 2022 Joe Hupcey Webinar
Dig a Pool of Specialized SystemVerilog Classes
SystemVerilog Oct 17, 2022 Chris Spear link

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

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