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September 2021 - Volume 17 Issue 2 (7)

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Show Less

August 2020

Verilog Basics for SystemVerilog Constrained Random Verification
SystemVerilog Aug 18, 2020 Dave Rich Webinar

July 2020

Understanding the SVA Engine Using the Fork-Join Model
SystemVerilog Jul 19, 2020 Ben Cohen Article
Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC
UVM - Universal Verification Methodology Jul 19, 2020 Kiran Malvi, Priyanka Gharat, Past Dean Prof Sastry Puranapanda - Silicon Interfaces® Article
PCIe® Simulation Speed-Up with PLDA PCIe® Controller for DMA Application
Verification IP Jul 19, 2020 Akshay Sarup Article
Extending SoC Design Verification Methods for RISC-V Processor DV
Verification IP Jul 19, 2020 Larry Lapides Article
Addressing VHDL Verification Challenges with OSVVM
VHDL 2008 Jul 19, 2020 Jim Lewis Article
Get Your Bits Together: SystemVerilog Structures and Packages
SystemVerilog Jul 14, 2020 Chris Spear Webinar
Simplifying Questa Usage and Deployment with Qrun
FPGA Verification Jul 09, 2020 Tom Kiley Webinar

June 2020

Introduction to Visualizer for the VHDL Users
Debug Jun 30, 2020 Rich Edelman Webinar
Introduction to Visualizer for the Verilog Users
Debug Jun 16, 2020 Rich Edelman Webinar
Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance
Functional Safety Jun 11, 2020 Jacob Wiltgen Session
Confronting Inevitability: Finding Clock and Reset Issues Before They Find You
Clock-Domain Crossing Jun 11, 2020 Chris Giles Webinar
Taking SystemVerilog Arrays to the Next Dimension
SystemVerilog Jun 05, 2020 Chris Spear Webinar
Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal
Formal Verification Jun 04, 2020 Mark Eslinger Webinar

May 2020

Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP
Verification IP May 28, 2020 Munish Goyal Webinar
Context-Aware Debug
Debug May 21, 2020 Rich Edelman Webinar
Productivity in the Questa Simulation Flow
FPGA Verification May 15, 2020 Gordon Allan Webinar
Optimizing Time to Bug
Planning, Measurement and Analysis May 15, 2020 Tom Fitzpatrick Webinar

April 2020

UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know
SystemVerilog Apr 10, 2020 Chris Spear Webinar
Code Generation Merging
UVM Framework Apr 01, 2020 Jonathan Craft pdf
Code Generation Merging
UVM Framework Apr 01, 2020 Jonathan Craft Session

March 2020

FPGA Verification Maturity: A Quantitative Analysis
FPGA Verification Mar 26, 2020 Harry Foster Webinar
Verify Thy Verifyer
UVM - Universal Verification Methodology Mar 01, 2020 Srinivasan Venkataramanan, Ajeetha Kumari - Verifworks Article
Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs
Formal Verification Mar 01, 2020 Tomáš Vaňák - Codasip Article
An Open Data Management Tool for Design and Verification
Verification Management Mar 01, 2020 Vishal Patel, Manoj Pandey - Arastu Systems Article

Osmosis 2024

Thursday, October 17th | Holiday Inn City Centre | Munich, Germany

DVCon Europe 2024

October 15th -16th | Holiday Inn City Centre | Munich, Germany

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

VA Live Seminar

Wednesday, November 6th | TopGolf | Austin, Texas

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Upcoming HBM4 Webinar

Wednesday, Oct 30th-9:00 AM PDT

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

Upcoming Questa Webinar

Wednesday, Nov 13th-8:00 AM PST

Simplify Scripting Environment using Qrun Capabilities in QuestaSim

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