1. Thursday, May 1st, 2025 | 9:30 AM - 3:30 PM US/Pacific

    osmosis Silicon Valley 2025

    The osmosis event series is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants.

  2. Tuesday, May 13th, 2025 | Munich, Germany

    User2User Europe 2025

    Join us in Munich, Germany, where peer-delivered technical sessions will be shared across a breadth of topics so you can explore new concepts or dive deep in your core area of expertise with fellow like-minded professionals.

  3. Tuesday, May 20th, 2025 | Santa Clara, CA

    User2User North America 2025

    Join us in Santa Clara, CA where you will have the opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens electronic design automation (EDA) tools.

  4. Wednesday, April 30th | 10:00 AM US/Pacific

    Ethernet 1.6T, Infiniband, UALink & UEC Verification for Next-Gen Connectivity

    This session introduces Avery Verification IP for Ethernet 1.6T, Infiniband, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity.

  5. Wednesday, May 21st | 08:00 AM US/Pacific

    Solving the Semiconductor Verification Crisis: From Problem to Productivity

    In this session, you will more about the challenges that are currently being faced by the digital design and verification industry and the steps we can take to mitigate some of these challenges.

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      A community of industry peers

      The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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      The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize.

  12. Welcome to Verification Academy

    1. About Us - Last Update 01-04-2024

    2. Who we are

      Welcome to the Verification Academy, a platform designed to help you develop the skills necessary to advance your organization's functional verification process. Our team comprises subject-matter experts in the industry who are dedicated to providing the necessary skills to mature an organization’s advanced functional verification process capabilities.

      Through a methodological bridge between high-level value propositions related to advanced verification technology and low-level details related to specific tool and verification language details, the team strives to offer a unique in-depth learning experience that is unlike anything in the industry.

      The Verification Academy also provides a wealth of resources, events, and tools to help verification engineers stay up-to-date with the latest trends and techniques in the field.

      Learn more about us
  13. About US Blocks

    1. What is advanced functional verification?

      Advanced functional verification is the process of testing and validating the functionality of a semiconductor chip design prior to its manufacture. It involves the use of specialized software tools and techniques to simulate and test the chip's behavior under different operating conditions and verify that it meets the required performance specifications.

      Advanced functional verification is critical in ensuring that the chip design is error-free and meets the required quality standards, which is essential in today's complex and fast-paced semiconductor industry.

      Learn more about verification
    2. Interactive Technologies - Last Updated 01/01/2024

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