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Interview with Abhi Kolpekwar
AI is Changing Verification
Join DV Digest and Abhi Kolpekwar and learn how scalable, intelligent verification strategies are addressing these modern complexity challenges through connected workflows, AI-enhanced automation, and data-driven insights.
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October 23rd | 0800 US/Pacific
Improving Verification Productivity Using Questa One Sim
This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim. We'll also showcase Questa One Sim cutting-edge debugging tools.
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November 5th | 0800 US/Pacific
Formal Verification of Synthesizable C++/SystemC Designs
Formal check tools are difficult to be analyzed on generated RTL (as the errors cannot be correlated to HLS source code) Catapult Formal/Onespin SystemC help to overcome this challenge. Under HLV there are several apps, to verify and clean C++ HLS code before running HL Synthesis and then apply equivalency between C++ and RTL to guarantee that golden C++ is equivalent with final RTL design. In this webinar, you will learn how to apply HLV tools for C++/SystemC designs.
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November 12th | 0800 US/Pacific
Don't Let VHDL Debugging Slow You Down! Use Questa One Sim
This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim. We'll also showcase Questa One Sim cutting-edge debugging tools.
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Recently published in the Verification Academy
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HLV: Formal Verification of Synthesizable C++/SystemC Designs and Prove Equivalency with RTL Code
Formal Verification Nov 05, 2025 Webinar -
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From Manageability to 3.0: Unlocking the Future with UCIe Verification
Verification IP Sep 26, 2025 link -
Pushing Boundaries: Smarter Verification for UCIe Multi-die Systems
Verification IP Sep 18, 2025 link -
From Novice to Expert: Your Tutorial Roadmap at DVCon Europe 2025
Machine Learning Sep 17, 2025 link -
Class is Back in Session this October: Verification Academy’s Cutting-edge Weekly Webinar Series
Simulation Sep 16, 2025 link -
Functional Verification Insights: A Conversation with Abhi Kolpekwar
Planning & Analysis Sep 15, 2025 link -
The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.
Simulation Sep 08, 2025 link -
Why First-Silicon Success Is Getting Harder for System Companies
Planning & Analysis Sep 03, 2025 link -
Siemens at DVCon India 2025: Driving the Future of Design and Verification
Planning & Analysis Aug 26, 2025 link -
Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching!
Planning & Analysis Aug 25, 2025 link -
SystemVerilog Transactions, UVM and C: Correlation in a Functional Verification Environment
SystemVerilog Aug 20, 2025 pdf
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More Discussions in the Forums
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UVM
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SystemVerilog
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Featured DAC 2025 Exhibitor Forum
Smart Verification for Modern Complexity
In this session, you will learn how scalable, intelligent verification strategies are addressing these modern complexity challenges through connected workflows, AI-enhanced automation, and data-driven insights.
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Explore learning topics
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UVMC
In today's complex and rapidly evolving world of electronic design and verification, verification engineers are constantly seeking innovative solutions to streamline their processes and improve productivity. One such solution that has gained considerable attention and recognition is UVM Connect. -
Low Power
Low Power verification enables early (RTL) verification of active power management applied to a complex design, to ensure that the power management architecture and behavior are correct and that the design will operate correctly under active power management. Power Aware techniques simplify the verification process through a comprehensive suite of static checkers for checking the consistency of the power management architecture and dynamic checks for automated error detection.Utilizing Low Power standards provide visualization of power management architecture and behavior, coverage data collection, and test plan generation for power states and state transitions. Based on the UPF for specification of active power management, Power Aware integrates well with other UPF-based tools to support multi-tool and multi-vendor low power design and verification flows. -
Questa Design Solutions
Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyzes code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules. -
UVM - Universal Verification Methodology
The Universal Verification Methodology (UVM) is a powerful framework for designing and verifying complex digital systems, offering significant benefits in terms of reusable and scalable testbenches. UVM promotes reusability by providing a standardized methodology for creating modular, configurable verification components. This modular approach allows engineers to develop testbenches using reusable building blocks, reducing redundancy and saving time.Furthermore, UVM enhances scalability, enabling easy adaptation to changing project requirements. As designs evolve, UVM's hierarchical and flexible architecture simplifies the addition or modification of testbench components, ensuring efficient and maintainable verification environments. Overall, UVM streamlines the verification process, promoting productivity and ensuring robust, adaptable testbenches. -
Verification IQ
Big data is transforming all industries, enabling them to innovate their products more rapidly and improve many aspects of our lives. EDA is powering these transformations. Verification needs to transform in step, so we can predict which test to run next, the root cause of a failure, and what stimulus is required. -
UVM Framework
The Universal Verification Methodology Framework (UVMF) is an advanced and comprehensive toolset that extends the capabilities of UVM, the Universal Verification Methodology. UVMF provides a robust and structured approach to verification, offering a wide range of pre-built components, utilities, and testbenches that accelerate and simplify the verification process.With UVMF's flexible architecture, verification engineers can effortlessly customize and integrate the components into their specific projects, fostering reusability and scalability. By leveraging UVMF, verification teams can significantly reduce development time, enhance collaboration, and ensure the delivery of high-quality, error-free semiconductor designs to meet the ever-increasing demands of the electronics industry. -
Assertions
A verification engineer plays a critical role in the development of complex electronic systems, ensuring that these systems meet the desired functionality and adhere to the design specifications. One powerful tool in the verification engineer's arsenal is the use of assertions. Assertions are statements or properties embedded within the verification environment that help identify design bugs and verify the correctness of the system. -
Coverage
Coverage metrics are crucial in digital design verification for ensuring the functionality, reliability, and quality of complex electronic systems. These metrics quantify the extent to which various aspects of the design have been tested, offering a measure of assurance that the design meets its specifications. Coverage metrics help identify untested or under-tested areas, enabling engineers to focus their efforts effectively, improve test plans, and uncover potential bugs or design flaws. They aid in risk mitigation, reducing the likelihood of costly post-production errors. Moreover, they enhance the overall efficiency of the verification process, making it more cost-effective and enabling faster time-to-market. In a world increasingly reliant on electronics, robust coverage metrics are an indispensable part of the verification process required for delivering safe and reliable digital products. -
Formal Verification
Formal verification is a topic area that encompasses a wide array of formal-based technologies and methodologies, including formal property checking, automatic formal apps, and sequential and logic equivalence verification. By employing mathematical models and logical reasoning, formal solutions scrutinize and validate complex systems, such as hardware circuits with the goal of enhancing reliability and eliminating design flaws. -
Acceleration
Verification is a critical phase in the design and development of digital systems, ensuring their correctness and functionality. Simulation has long been the primary technique used for verification, enabling engineers to model and test designs using software-based models.However, as designs have grown increasingly complex, traditional simulation methods have proven to be insufficient in meeting the demands of modern verification. Particularly with the emergence of hardware/software co-verification requirements. This has led to the emergence of emulation as a more efficient and effective approach that combines simulation with hardware acceleration techniques. -
Verification Academy Live
In these one day seminars, attendees will learn new technologies and techniques that you can adopt today to increase your verification productivity. -
Portable Stimulus
The Portable Stimulus Standard (PSS) represents a transformative advancement in verification methodologies. At its essence, it is a standard that allows for the specification of verification intent a single time followed by its reapplication across various platforms, tools, and verification stages. Developed by the Accellera Systems Initiative, Portable Stimulus offers a unified framework for creating verification tests that can be effectively utilized across multiple verification environments and abstraction levels. -
FPGA Verification
FPGA (Field-Programmable Gate Array) verification, including methods like simulation and formal verification, is invaluable for ironing out design issues before deploying hardware in the lab. Simulation allows engineers to comprehensively test the FPGA design under various conditions, helping detect and rectify potential bugs and ensuring functionality. By conducting thorough FPGA verification, costly and time-consuming hardware iterations are minimized, significantly reducing the risk of errors and shortening the time-to-lab phase. This approach ultimately leads to more efficient development, lower expenses, and a faster path to achieving operational hardware. -
Clock-Domain Crossing
Designers increasingly use advanced multi-clock architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has more than one clock domain does not accurately model the silicon behavior related to the transfer of data between asynchronous clock domains. As a consequence, simulation does not accurately predict silicon functionality, risking show-stopper bug escapes due to metastability.Metastability is a phenomenon that can cause system failures in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This topic area focuses on advanced techniques to find clock-domain crossing errors before they escape into silicon. -
Functional Safety
Functional safety verification in digital design and integrated circuit design is crucial for ensuring that electronic systems operate reliably, especially in safety-critical applications like areospace, automotive, medical devices, and industrial control systems. It focuses on identifying and mitigating potential hazards and failures that could lead to catastrophic consequences.By rigorously verifying safety-critical designs, we reduce the risk of system malfunction or failure, safeguarding human lives and valuable assets. This process involves thorough analysis, testing, and adherence to industry standards such as ISO 26262 and DO-254.In a world increasingly dependent on digital technology, functional safety verification is paramount to prevent disasters and maintain trust in electronic systems. -
Planning, Measurement and Analysis
Planning, measurement, and analysis are critical in digital design and verification as they provide a structured approach to ensure the reliability and functionality of complex electronic systems. Planning sets clear objectives and strategies for verification. Metrics offer quantifiable data to assess progress and completeness, helping to identify untested areas. Analysis enables the detection of design flaws and bugs.Together, they enhance efficiency, reduce risks, and accelerate time-to-market, ensuring the final product meets specifications. These processes are indispensable for achieving high-quality, reliable, and compliant digital designs in an increasingly competitive and fast-paced technology landscape. -
Verification Management
Verification is an essential step in the design and development process of complex systems, ensuring that the final product meets the specified requirements and functions as intended. With the increasing complexity of modern systems, the role of verification engineers has become more critical than ever.To streamline and optimize the verification process, verification management techniques have emerged as a valuable approach. In this article, we will explore what verification management is and how verification engineers can leverage this technique to enhance their efficiency and effectiveness. -
Standards
Electronic Design Automation (EDA) standards, including SystemVerilog, VHDL, UVM, UPF, and others, offer significant benefits in the development of electronic systems. These standards provide a common framework and language for designers and verification engineers, facilitating collaboration, improving design quality, and accelerating the design process. They enable the creation of robust, interoperable, and reusable designs, ultimately resulting in more efficient and reliable electronic systems. -
Machine Learning
Machine learning (ML) has emerged as a powerful tool in the field of verification engineering, revolutionizing the way we validate and verify complex systems. Verification engineers are responsible for ensuring that hardware and software systems meet their specifications and perform reliably. In this context, machine learning offers a fresh approach to address challenges and enhance the verification process. -
VHDL 2008
VHDL (VHSIC Hardware Description Language) is a powerful and widely used hardware description language. Introduced as IEEE 1076-2008, VHDL has become a crucial tool for electronic engineers and researchers, facilitating the design and modeling of digital and analog systems. It allows designers to create both RTL (Register-Transfer Level) and structural representations of desired systems by employing constructs such as processes and variables.VHDL 2008 is the most widely used and supported version of the language, which was published by the IEEE in 2007. This updated version brings several enhancements and new features to the language, making it more expressive, efficient, and user-friendly. -
Reset-Domain Crossing
The high-level complexities of modern System On Chip (SoC) designs have created a complex architecture of multiple asynchronous reset sources. It is imperative to ensure that the design is reset accurately under all modes of operation. Such complex reset interactions asserting at the transmitting flop may violate setup and hold time considerations in receiving flop in different asynchronous reset domain and cause metastable data at the output of receiving flop resulting in reset domain crossings.A comprehensive and precise analysis is required to not only identify such crossings causing real and critical issues but also avoid reporting false bugs. This topic area focuses on advanced techniques to find reset-domain crossing errors in efficient way before they escape into silicon. -
Verification IP
Avery Verification IP (VIP) plays a crucial role in ensuring the success of complex semiconductor designs by offering a wide range of benefits and a compelling value proposition. Avery Verification IP provides pre-verified and reusable components, tools, and methodologies that enable efficient and thorough verification of electronic designs. -
Debug
Debugging is a critical aspect of the digital design and integrated circuit design process. It ensures that the designed system or chip functions as intended, identifying and rectifying errors, glitches, and unforeseen issues. Effective debugging saves time and resources, preventing costly mistakes from reaching the final product.It also enhances product reliability, crucial in safety-critical applications, and reduces post-production maintenance. Debugging tools and techniques are essential for engineers to pinpoint and address issues, making the design process more efficient and leading to the creation of high-quality, dependable digital systems and integrated circuits. -
Simulation
Simulation plays a pivotal role in the digital design and verification process. Its primary purpose is to validate whether the design being created functions according to the specified requirements. By running simulations early in the design phase, potential issues can be identified, thus minimizing the need for extensive code revisions. Simulations can be performed at different levels of abstraction and at various stages throughout the design process. -
SystemVerilog
SystemVerilog is a hardware description and verification language that combines elements from a number of different language technologies into a unified simulation and synthesis platform. It provides a robust set of features and constructs specifically designed for the verification of complex digital designs including object-oriented programming, assertions, functional coverage and constrained random stimulus generation. As a verification engineer, understanding and utilizing SystemVerilog can greatly enhance your ability to effectively test and verify hardware designs.
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What we offer
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A community of industry peers
The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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In-depth learning resources
The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize.
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Welcome to Verification Academy
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About Us - Last Update 01-04-2024
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Who we are
Learn more about usWelcome to the Verification Academy, a platform designed to help you develop the skills necessary to advance your organization's functional verification process. Our team comprises subject-matter experts in the industry who are dedicated to providing the necessary skills to mature an organization’s advanced functional verification process capabilities.
Through a methodological bridge between high-level value propositions related to advanced verification technology and low-level details related to specific tool and verification language details, the team strives to offer a unique in-depth learning experience that is unlike anything in the industry.
The Verification Academy also provides a wealth of resources, events, and tools to help verification engineers stay up-to-date with the latest trends and techniques in the field.
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About US Blocks
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What is advanced functional verification?
Learn more about verificationAdvanced functional verification is the process of testing and validating the functionality of a semiconductor chip design prior to its manufacture. It involves the use of specialized software tools and techniques to simulate and test the chip's behavior under different operating conditions and verify that it meets the required performance specifications.
Advanced functional verification is critical in ensuring that the chip design is error-free and meets the required quality standards, which is essential in today's complex and fast-paced semiconductor industry.
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Interactive Technologies - Last Updated 01/01/2024
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