Seeking Suggestions to Constraint Addresses to be Non-Overlapping

SystemVerilog
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1

Hi All,
I have the following code

bit [03:0] axlen;
bit [31:0] wr_data[];
logint unsigned ind[$]; // Starting address

task body();

 if( $test$plusargs("BURST") ) begin
   if( std::randomize(axlen) with { axlen inside {[1:15]} ; }  )  // Max of 16 beats
      `uvm_error(get_type_name(),$sformatf("Randomization Failed"))
 end

if( std::randomize(ind,wr_data) with { ind.size() == 100;
                                     wr_data.size() == (axlen+1)*4 ; // Each beat is 128-bit

                                     foreach( ind[i] ) 
                                   {  ind[i][1:0] == 0 ; // Aligned Address
                                      ind[i] inside {[0:32'd393215]} ;
                                      // 4K boundary constraint
                                   ( (ind[i] << 2) % 4096 ) + ( 16 * (axlen+1) ) <= 32'd4096 ;
                                   }
                                      } )
      `uvm_error(get_type_name(),$sformatf("Randomization Fails"))
                                   
endtask

One possibility with the above constraint is that the Indexes could be overlapping
Eg: axlen is constrained to be 1 ( i.e 2 beats ) so if ind[0] is constrained to be 'h100,
I don’t want any of the remaining indexes in the burst to be b/w 'h100 to 'h107
The nearest lower value would be 'h92 ( so that 'h92 +: 4*(awlen + 1) would be 'h99 )
The nearest upper value would be 'h108 ( so that 'h108 +: 4*(awlen + 1) would be 'h10F )

Seeking suggestions to constraint each ind to be non-overlapping

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