How to use multiple sequences to override base test

[proc123]

Hello,

I have 2 sequencers that I am using in a fork…join_none. Now I have to override both the base sequences when I am running the test, how can I achieve that?

I have +uvm_set_type_override=base_sequence1,user_sequence in my run script.
Can I add another +uvm_set_type_override=base_sequence2,user_sequence?

Thanks

[MichaelP]

Are you using 2 sequenceRs or sequences in your fork…join_none?

Did you try to have multiple command line arguments: +uvm_set_type_override
one per each override?
It should work fine, since you are overriding 2 different base_sequences1/2.

[proc123]

@MichaelP I am using 2 sequencers in fork…join_none. I tried to override in my run script, but it would need me to run the base sequences all the time. Is it possible to run only 1 sequencer at a time and run the other one as a reactive component.

[MichaelP]

It would be hard to help you without seeing the code you wrote.
Could you add it using EDA playground?
Or paste it here?

And please add the errors/warnings you receive when compiling, or run-time errors.

[proc123]

virtual task run_phase(uvm_phase phase);

base_seq1 seq1;
base_seq2 seq2;

seq1 = base_seq1::type_id::create(seq1);
seq2 = base_seq2::type_id::create(seq2);

fork 
seq1.start(seqcr1);
seq2.start(seqcr2);
join_none

endtask

in my run_script - …/simv -l sim.log +uvm_set_type_override=base_seq1,user_seq +uvm_set_type_override=base_seq2,user_seq

Errors I am seeing when trying to run only 1 sequencer at a time -
UVM_ERROR @ 0 ns: reporter [UVM_CMDLINE_PROC] Invalid setting for +uvm_set_type_override=base_seq2, setting must specify <requested_type>,<override_type>[,]

[MichaelP]

@proc123

in my run_script - …/simv -l sim.log +uvm_set_type_override=base_seq1,user_seq +uvm_set_type_override=base_seq2,user_seq

Did you pay attention that your <override_type> in both cases is user_seq?
What is the inheritance tree of: user_seq?

Could you please add the code of user_seq?

And I think you are missing “” in the create method, see code below:
seq1 = base_seq1::type_id::create(“seq1”);
seq2 = base_seq2::type_id::create(“seq2”);

Please try it, the first argument of create method is name of type string.

[MichaelP]

Please format you code with markdown tags.

You could read about it in the post below:

Please format your code with markdown tags

See Formatting in Posts for all formatting options Your source code will be much easier to read when it is formatted nice and pretty like this: class packet; rand bit [31:0] address; rand bit [7:0] length; rand bit [7:0] data[]; constraint max_length { length == data.size(); } endclass: packet instead of: class packet; rand bit [31:0] address; rand bit [7:0] length; rand bit [7:0] data; constraint max_length { length == data.size(); } endclass: packet All you ha…

[proc123]

Sorry, both are not user_seq, it should be user_seq1 and user_seq2.

[MichaelP]

And I think you are missing “” in the create method, see code below:
seq1 = base_seq1::type_id::create(“seq1”);
seq2 = base_seq2::type_id::create(“seq2”);

Please try it, the first argument of create method is name of type string.

[proc123]

@MichaelP thank you fixed it, but I still see the same issue

[MichaelP]

what is the error you receive now?
please copy-paste it here.

[proc123]

I see this when I try to override only 1 sequence. Do I need to override both the sequences all the time?

UVM_ERROR @ 0 ns: reporter [UVM_CMDLINE_PROC] Invalid setting for +uvm_set_type_override=base_seq2, setting must specify <requested_type>,<override_type>[,]

[MichaelP]

Further steps:

1. First try to run your test without any overrides from the command-line.
   Just to see your basic code is working.
2. Use only 1 override using the command-line.
   Do it twice to see it works for both sequences separately.

[proc123]

@MichaelP thanks for your help. It worked.

[MichaelP]

@proc123 You are welcome.
What was the issue/problem eventually?

What did work?