Query on Register wr/rd verification by taking security state into consideration

UVM
1

I’m working on a complex HPC-SOC project Memorymap(register wr/rd) Verification with UVM-RAL. It has multiple processors.

I’ve the below queries :

  1. Let’s say a peripheral is marked as “Secure” in the memorymap XLS given by Design Team, this means that only the “Secure” security state has access to that field. When the UVM-RAL attempts to access this field from a “Non-secure” state, it will either be blocked or an error will be reported. How to verify this in checkers in easy way?

Ex: I’m trying to access secure region from non-secure region. I’m expecting DECERR from DUT, how RAL comes to know that we initiated a non-secure transfer and expected response is DECERR and make the test as PASS without throwing an UVM_ERROR. How to write checkers for them in easy way?

  1. Earlier in simple IP and SoC based design register wr/rd Verification, I used set_check_on_read(1) to verify the mirror value with desired value comparison. But, here in this complex HPC-SOC reg wr/rd verification, along with data comparison, I also need to take care of secure, nonsecure transfers(ie., security states) & also check whether the received response is proper or not to make the test PASS/FAIL. So, here can I use set_check_on_read(1) or I need to write any checkers on my own?

  2. Is there any simple/easy approach to verify these kind of complex SOC register wr/rd by taking “security” state and “expected response” also into consideration with UVM-RAL?

2

I do not know how your safety guard is implemented, but I’d try to use backdoor access for your registers.

3

How using “backdoor access” is supposed helping with handling accesses to “Secure” area, when trying to access it from a “Non-Secure” state?