"David is an Eagle Scout and our troop's Senior Patrol Leader... I'm the Scoutmaster... What that really means is that David and I have to work together to make sure that the troop functions well as a unit..."
Hello, and welcome to our Autumn, 2013 edition of Verification Horizons. I love autumn here in New England. The air is crisp and clean, the trees are turning beautiful colors, and it's time for David and me to begin another year of camping and other fun activities with the Boy Scouts. David is an Eagle Scout and our troop's Senior Patrol Leader, which means that he's in charge of running troop meetings and campouts. I'm the Scoutmaster, so it's my job to support him and the other boys, make sure they're adequately trained and keep them safe. What that really means is that David and I have to work together to make sure that the troop functions well as a unit and that everyone has fun. Those of you with teenage sons may recognize the potential pitfalls of such an arrangement, but so far we've done pretty well, if I do say so myself. You'll see these ideas of teamwork, planning and safety in our articles for this issue.
We start with two articles based on papers being presented at ARM TechCon. The first is a case study of a successful collaboration with Altera in "Software-Driven Testing of AXI Bus in a Dual Core ARM System" in which our friend Galen Blake at Altera shows how they used Questa to create abstract stimulus specifications that they were able to use in different contexts, including software, as they verified their system. Combined with Questa's intelligent automation, they were able to generate traffic coordinated across the interfaces and the processor software to check everything from protocol compliance to fabric performance.
In "Caching in on Analysis," my colleague Mark Peryer describes Questa SLI, our new technology for verifying system-level interconnect in both simulation and emulation. Initially providing VIP and automation targeted for cachecoherent protocols like ACE and CHI, Questa SLI provides stimulus generation, instrumentation, visualization and analysis of system-level behavior and performance. Given how complex cache-coherent interconnect fabrics have become, and how critical they are to SoC functionality, I think you'll easily see how important a tool like this can be.
VIP is always an important part of a verification environment. In "DDR SDRAM Bus Monitoring using Mentor Verification IP," by my colleague Nikhil Jain, we see how Mentor VIP can be used in passive mode to monitor and check protocol behavior. By including coverage collection and assertions, Mentor VIP gives you everything you need to check a particular protocol, and this article shows how effective it can be.
Our next article shares another success by our friends at STMicroelectronics. In "Simulation + Emulation = Verification Success" you'll see how they took advantage of Mentor VIP's multi-platform compatibility to simplify their integration of emulation in their verification environment. Even with multiple teams in different locations, they were able to use the setup to do software-driven verification with the testbench in the simulator and the design in the emulator.
If you're using code coverage as part of your verification process, you'll want to check out Roger Sabbagh's article, "Life Isn't Fair, So Use Formal." We all know how hard it is to reach that last 10% of code coverage, usually requiring manual review of coverage holes and having to decide which exceptions are acceptable.