Verification Horizons Complete Issue:
Verification Horizons Articles:
by Tom Fitzpatrick, Editor and Verification Technologist, Mentor Graphics
Welcome again to Verification Horizons.
In the last issue I wrote about my son graduating high school and my hopes for him as he begins his college career. Well, he's been at school (and away from home) for over six weeks at this point and seems to be off to a great start. We're going to visit him this weekend for the first time, and we're really looking forward to seeing him.
As he was preparing for college, my wife and I explained to him the importance of time management since, compared with high school where his days were pretty well defined from 7:00 AM until 3:00 PM (and sometimes later), he'd have much more free time and would have to use it effectively. When we spoke to him a few weeks ago, he told us that we were wrong because he really doesn't have much free time at all. Turns out he wasn't considering all of his extra-curricular activities, including playing the saxophone in the Jazz Ensemble and Pep Band and joining the Ultimate Frisbee team, to be "free time." Yes, his schedule is pretty packed, but he's having fun and still getting his homework done on time, so things are good.
by Nitish Goel, Mentor Graphics
With ever increasing design complexities, ASIC and SoC (system on chip) design verification has become the biggest challenge for design and verification engineers. Various Hardware Description Languages (HDLs), like Verilog, VHDL, and SystemVerilog, and verification methodologies, like UVM and OVM, have facilitated the task of verifying designs. Despite this, bugs are still missed in the verification/validation phases, which eventually leads to a re-spin of the entire chip. Verification environments that assist with the right set of assertions and coverpoints not only increase the verification efficiency, but also aids the verification engineer to ensure that the functionality of the IP has been met according to design specifications. This article gives insight into how to capture assertions and coverpoints and how they should be written in order to achieve maximum design verification robustness.
by Gyanaranjan Khuntia and Rajat Rastogi, Mentor Graphics
Optimization of servers in terms of speed and reliability needed a high speed protocol to send the data from end to end. PCIe provides lower latency and higher data transfer rates than parallel buses, such as PCI and PCI-X. With PCIe, data center managers can take advantage of highspeed networking across server backplanes and connect to Gigabit Ethernet, RAID and Infiniband networking technologies outside of the server rack. For laptops and mobile devices, mini PCIe cards can be used to connect wireless adaptors, solid state device storage and other performance boosters. PCIe can scale from one to thirty-two separate lanes, which can support up to 512 Gbps (16 Gbps*32) in Gen4 speed.
by Suraj Parkash Gupta and Zeeshan Yousuf, Mentor Graphics
The standard USB connector that we are most familiar with is USB Type-A. Even as the USB data interface moved from USB1 to USB2 and then to USB3, the connector has remained the same. It is a massive connector and plugs in only one way.
These limitations are resolved by the USB Type-C connector. In addition to its flexibility and small size, the USB Type-C connector handles the larger power requirements of today's USB ports. It also supports a variety of different protocols using "alternate modes," which allows using adapters that can output HDMI, VGA, Display Port, or other types of connections from a single USB port.
by Saumya Agrawal, Mentor Graphics
Automotive vehicles are not only fast moving, but also have various systems comprising a variety of advanced technologies. Increasing complexities of these systems need much more sophisticated components and interactions. Amongst the various standards that target the automotive IP section, CAN holds a unique place. CAN (controller area network) is a communication protocol which uses a single, shared serial bus and supports distributed real time multiplexing for use within a variety of road/space applications. Various nodes that connect on the bus can have different oscillator frequencies but all coordinate in a manner such that a network-wide time quantum and, eventually, bit time is achieved. Designing of such a system is sophisticated, but the verification of a CAN node or CAN system brings many more challenges and complications. This article explains the challenges in the verification of a CAN node and how CAN Questa® Verification IP combats those.
by Vijay Chobisa, Mentor Graphics
The way companies use hardware emulation has changed. Historically, emulators were used in a lab, at one location, executing one job at a time. Because of this, an emulator often sat idle. In this scenario, project scheduling for the emulator was done manually by allocating fixed time slots to project teams. An inherently inflexible and inefficient way to manage a valuable resource, especially for global teams.
Emulators are not confined to this arrangement anymore. They are now managed as a corporate-wide shared resource in a datacenter. Initially, the efforts to meet the requirements for a shared resource depended on standard job management software, such as LSF and Sun Grid. But these approaches treated emulators like any other hardware in a datacenter. The truth is that emulators are far more complex and specialized than general purpose systems. Every emulation job is different in terms of size, duration, verification requirements and priority.
by Progyna Khondkar, Mentor Graphics
Multivoltage (MV) based power-ware (PA) design verification and implementation methodologies require special power management attributes in libraries for standard, MV and Macro cells for two distinctive reasons. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distinctive attribute between a special MV cell and a regular standard cell. The special MV cells include isolation (ISO), levelshifters (LS), enable level-shifter (ELS), always-on buffers (AOB), feed through buffers or repeaters (RPT), diode clamps, retention flops (RFF), power switches (PSW), multiand single-rail macros. This article describes the standard requirements for libraries and processing mechanism in Questa® PA-SIM from UPF-based PA verification perspective.
by Umesh Patel and Dhaval Shah, Arastu Systems Pvt. Ltd.
The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs. Pre-silicon verification for first-pass success using current verification approaches is just not enough. A unique approach is needed that not only verifies the design faster but also achieves consistent results. Intelligent testbench with automation is the answer to today's manual verification approach.
ASICs today demand high-bandwidth operations; which in turn demand high bandwidth on a system memory bus, like a DRAM interface bus. It is imperative that a comprehensive verification plan also includes verification for performance and power along with functional features. Having a large number of variables makes verification more complex. But this adds confidence in ASIC/SoC completeness for an end user's application. In order to achieve high system performance in any ASIC/ SoC, DRAM bus bandwidth utilization is equally important for that system.