Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology. To celebrate the 10th anniversary of the UVM, I would like to take the opportunity to reflect on how well it has achieved its objectives and what its future might hold.
I am old enough to remember the days before verification methodologies. My first experience writing a testbench was to write parallel patterns that were fired at a design in a simulator, where every