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With more emphasis within the electronics industry on high-performance and shorter time to market, the need for high-confidence and high-quality end-to-end verification is becoming more and more important. This is especially true on the heavily optimized arithmetic datapath blocks most used in modern compute and neural network applications. Missed bugs can delay projects and be costly to reputations, and, at the very least, be likely to sap performance.
Given that physical hardware is inherently fixed and unchangeable, it is extremely hard, if not impossible, to correct bugs and design faults after release. As such, the verification of hardware IP well before the move to full silicon tape-out is an established and widespread practice. A
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