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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • March 2015
  • PowerAware RTL Verification of USB 3.0 IPs

PowerAware RTL Verification of USB 3.0 IPs

Verification Horizons - Tom Fitzpatrick, Editor

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PowerAware RTL Verification of USB 3.0 IPsby Gayathri SN and Badrinath Ramachandra, L&T Technology Services Limited

INTRODUCTION

Power management is a major concern throughout the chip design flow from architectural design to RTL implementation and physical design. Multi-power domain SoCs are complex and present new integration and verification challenges because many blocks have different operating modes at different voltages, different clock period and duty cycles of each block being awake, asleep or in shutdown mode. USB 3.0 or USB 2.0 Lower Layer resides in an always on power domain. This block has to be powered-on always for normal USB functionality and also to initiate suspend and wake-up sequences. If Link settles in USB 2.0 mode, USB 3.0 Lower Layer can be powered off. If

...

Table of Contents

Verification Horizons Articles:

  • Welcome to the DVCon 2015 issue of Verification Horizons

  • Does Design Size Influence First Silicon Success?

  • Successive Refinement: A Methodology for Incremental Specification of Power Intent

  • PowerAware RTL Verification of USB 3.0 IPs

  • Hardware Emulation: Three Decades of Evolution

  • Evolving the Use of Formal Model Checking in SoC Design Verification

  • Small, Maintainable Tests

  • Functional Coverage Development Tips: Do's and Don'ts

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