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by Samrat Patel & Vipul Patel, eInfochips
INTRODUCTION
The fundamental goal of a verification engineer is to ensure that the Device Under Test (DUT) behaves correctly in its verification environment. As chip designs grow larger and more complex with thousands of possible states and transitions, a comprehensive verification environment must be created that minimizes development effort. To minimize effort, functional coverage is used as a guide for directing verification resources by identifying tested and untested portions of the design. The approach should give any verification engineer confidence in DUT functionality.
Functional coverage is a user-defined coverage which maps each functionality defined in the test plan to be tested to a
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