Using Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
IEEE 1149.1-2013 is not your father's JTAG. The new release in June of 2013 represents a major leap forward in standardizing how FPGAs, SoCs and 3D-SICs can be debugged and tested. The standard defines register level descriptions of on-chip IP with operational descriptions via the new 1149.1 Procedural Description Language.1, 2, 3
Full-access members only
Register your account to view Using Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.