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The size and complexity of designs, and the way they are assembled, is changing the clock-domain crossing (CDC) verification landscape. It is now common for these complex SoCs to have hundreds of asynchronous clocks.
As CDC signals can lead to metastability, CDC metastability issues have become one of the leading causes of design re-spins. This trend has made CDC verification an even more critical step in the design verification cycle than before. Naturally, this requires more time and effort to verify CDC issues and poses multiple challenges for CDC verification at the SoC level.
There is an urgent need to move beyond the traditional, flat CDC verification approach. Flat CDC runs on an SoC are performance intensive, time-consuming, ...
