Design complexity is increasing proportionally with advancing technology. Reusing the same design in different applications and for multiple configurations are ways to deal with this complexity. Often this leads to the addressable registers in a design becoming more complex as well to support a multitude of functionalities.
Unlike simple addressable registers, complex addressable registers are not easy to implement in UVM and RTL using a simple script or an off-the-shelf generator. These complex addressable registers have special functionalities based on the particular application and are used to control various aspects of the design.
Often such registers are used in mission-critical applications. If a designer uses a simple script to create the RTL, they will need to change the RTL and UVM code manually to describe the complex registers, then re-simulate and verify the RTL.
Additionally, complex registers may have side-effects. They may interact with other register fields or hardware signals, and they may have parameterized fields and their width may be wider than the software bus, making it non-atomic to read/write.
In this article, we will discuss some complex registers that we have seen our customers use in mission-critical applications.
The following register types are discussed:
- Memory-based registers
- Trigger buffer registers
- Interrupt registers
- Lock registers
- Triple modular redundancy registers
MEMORY BASED REGISTERS
Memory is a continuous space for reading and writing the data with a different location depth. Memory locations can be used for multiple purposes besides storing data. With the scope of applications increasing, it’s not only the master that writes and reads the memory with a bus function model. The memory can also be read and written through virtual registers. Each of the memory based virtual registers is mapped to a specific location of the memory.
The memory-based registers can also be used as counters that can be preset or reset from other registers and that can access memory.
Figure 1 - Block Diagram — Virtual Registers:
The functioning of virtual registers can be explained using this block diagram. A RAM is attached to the bus slave via a memory interface. SW is the master side interface with the AXI bus (any other bus can be used). VirtualRAMRegGrp is a group of virtual registers with a number of registers either the same as memory depth or a portion of memory. Memory can either transact with the master via a bus or can transact with the virtual register group. In a testbench (UVM), the virtual registers are mapped to the RAM. When we write in the virtual register, the corresponding memory location is also updated and we can read the same data from the memory location. In the same way, if we write data in a memory location, we can read the same data from a corresponding virtual register. Thusly, an alternative way of transacting with the memory is achieved by using virtual registers.
Application: This is useful for application programmers who find it easy to access memory locations through relevant named registers. It also helps in creating a UVM testbench where we need to edit registers or memory via other virtual registers.
TRIGGER BUFFER REGISTERS
Sometimes it is required that a register with size greater than the bus width is written and read as one atomic unit from the hardware side. Such a register is written/read sequentially from the software side. This can be achieved by creating an N-register buffer in the memory space that is associated with a trigger event.
When the trigger event occurs, the write/read happens to/from the buffer to the actual register that is available to the hardware side. The trigger event can be a read/write to either the Least Significant or the Most Significant register.
Application: An application of a trigger buffer register is in counters. The up/down counter with size equal to the maximum register width at the threshold condition (generates carry for up counter or borrows one bit for down counter) may need one or more other bits that act as a trigger.
Designs often need interrupt signals for various reasons; e.g., software can disable or enable various blocks of logic when an error occurs. An interrupt is a signal generated and sent to the processor by hardware or software indicating an event that needs attention. The processor responds to it by suspending its current activities, saving its state, and executing a program called an Interrupt Service Routine (ISR) to deal with the event. The event is temporary: after the completion of the ISR, the processor resumes execution from the previously saved state.
Designs also need "halt signals" to halt the processor (i.e., idle state) at its normal completion of the program until the next interrupt is fired. Mostly used in debugging the processor, a halt signal is generated by external devices.
For a design to generate an interrupt signal, it must contain a set of registers that provide some logic for generating interrupts. These registers are identified as status, pending, enable, and mask register.
The status register saves/holds/contains the interrupt, which indicates whether an interrupt exists or not. This register has read and write permissions from the software side, but on the hardware side it is only a read with write 1 to clear.
The enable register is a gate for the propagation of interrupts inside the design. This register is readable and writeable from the software or hardware side.
The pending register contains the update of the interrupt as to whether an interrupt is active or not. The pending register is ANDing of status and enables register.
The mask register is used to disable the register interrupt. It works just the opposite of the enable register. If the mask register bit is high, then the interrupt is disabled.
The priority of mask and enable registers is user-defined or application based. The interrupts are processed in channel form; i.e., a corresponding bit of each of the above registers indicates one channel of an interrupt.
Application: Interrupts are used in various design applications; such as disk I/O, debug, power-off, and system timers.
The software writes access of a register or a register field can be locked based on the value of another register field. Or it can be locked based on an expression consisting of different register fields or some external signal declared as input in the signals table. Such a register for which the write access is locked is a "lock register."
The locked register can be locked through an expression of multiple registers or fields. If the expression is true, then the register, which is otherwise a read-write register, becomes read-only.
Figure 2 - Read-Write Register:
In the diagram above, there are two registers: RegA and RegB. By using the lock concept, RegB is locked by the data of RegA with a logic function. The lock logic is dependent on the data of RegA. So RegA is limiting the access of RegB register.
Application: Some complex designs where one register’s data affects another’s control logic.
Triple Modular Redundancy Register
Corrupted data in critical applications can lead to a disaster. Designers need to be proactive in ensuring accurate and correct data for mission critical designs. Sometimes they must add extra code to prevent this data corruption. If the registers already have a mechanism to prevent this corruption, then designers can be sure to have a failsafe design.
Triple Modular Redundancy (TMR) is a mitigation technique to protect digital logic from a Single Event Update (SEU). It is a voting concept for resolving errors in the design.
Figure 3 - Design Ouput:
The output of the above design is dependent on two or more of the same input signals; hence this is called a voting system. Here we have three registers to do the same task with the registers’ data being I1, I2, and I3. All registers are derived from the same input signal and then a logic is added for voting the data of registers before its output goes to the other design’s fan-in.
Application: TMR is used in mission-critical applications such as space (satellite) and defense (missile).
Design and verification engineers can use complex addressable registers in a simple way to resolve their problems related to design (RTL) and testbench (UVM) complexity. Special complex registers provide easy, abbreviated code and a convenient solution to create designs that are accurate and correct by construction.
We simulated our designs using Mentor’s Questa® 10.7 and found it helpful, proficient, easy to use, and easy to maintain. I personally like the dataflow window, which helps in debugging.
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