by Lior Grinzaig, Verification Engineer, Marvell Semiconductor Ltd.
Long simulation run times are a bottleneck in the verification process.
A lengthy delay between the start of a simulation run and the availability of simulation results has several implications:
Code development (design and verification) and the debug process are slow and clumsy. Some scenarios are not feasible to verify on a simulator and must be verified on faster platforms — such as an FPGA or emulator, which have their own weaknesses. Long turn-around times. Engineers must make frequent context-switches, which can reduce efficiency and lead to mistakes.
Coding style has a significant effect on simulation run times. Therefore it is imperative that the code writer