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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • June 2015
  • Accelerating RTL Simulation Techniques

Accelerating RTL Simulation Techniques

Verification Horizons - Tom Fitzpatrick, Editor

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Accelerating RTL Simulation Techniquesby Lior Grinzaig, Verification Engineer, Marvell Semiconductor Ltd.

Long simulation run times are a bottleneck in the verification process.

A lengthy delay between the start of a simulation run and the availability of simulation results has several implications:

Code development (design and verification) and the debug process are slow and clumsy. Some scenarios are not feasible to verify on a simulator and must be verified on faster platforms — such as an FPGA or emulator, which have their own weaknesses. Long turn-around times. Engineers must make frequent context-switches, which can reduce efficiency and lead to mistakes.

Coding style has a significant effect on simulation run times. Therefore it is imperative that the code writer

...

Table of Contents

Verification Horizons Articles:

  • Welcome to our once-again-super-sized DAC summer edition!

  • Verifying Airborne Electronics Hardware: Automating the Capture of Assertion Verification Results for DO-254

  • DO-254 Testing of High Speed FPGA Interfaces

  • Formal and Assertion-Based Verification of MBIST MCPs

  • Starting Formal Right from Formal Test Planning

  • Reuse MATLAB® Functions and Simulink® Models in UVM Environments with Automatic SystemVerilog DPI Component Generation

  • Intelligent Testbench Automation with UVM and Questa®

  • Unit Testing Your Way to a Reliable Testbench

  • Hardware Emulation: Three Decades of Evolution – Part II

  • Accelerating RTL Simulation Techniques

  • Emulation Based Approach to ISO 26262 Compliant Processors Design

  • Resolving the Limitations of a Traditional VIP for PHY Verification

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