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by Mihajlo Katona, Head of Functional Verification, Frobas
In recent years a number of different verification methodologies were developed to ease the process of pre-silicon verification of ASIC designs. Usually developed by EDA tool vendors, these methodologies often were not compatible with tools from different vendors. With the appearance of the Open Verification Methodology (OVM), which works best with SystemVerilog testbenches, verification became more and more standardized. OVM gave way to the Universal Verification Methodology (UVM), which is now an official Accellera standard supported by all EDA tool vendors.
Developing UVM-based testbenches from scratch is a time consuming and error-prone process. Engineers have to learn object
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