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by Eldon Nelson M.S. P.E., Verification Engineer, Micron Technology
SystemVerilog has the concept of covergroups that can keep track of conditions observed during a simulation. If you have a single instance of a covergroup in your design, you don't need to deal with merging coverage across all of the instances of that covergroup. If you do have multiple instances of a covergroup and want to merge coverage, there are implementation details that can make a big difference on what information you will be able to collect.
An incorrect application of a covergroup might collect extraneous information that slows down the simulation and the merging process. Or, an incorrect application of a covergroup could result in covergroups that cannot be
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