by Samrat Patel, ASIC Verification Engineer, and Vipul Patel, ASIC Engineer, eInfochips
A verification engineer's fundamental goal is ensuring that the device under test (DUT) behaves correctly in its verification environment. Achieving this goal gets more difficult as chip designs grow larger and more complex, with thousands of possible states and transitions. A comprehensive verification environment must be created that minimizes wasted effort. Using functional coverage as a guide for directing verification resources by identifying tested and untested portions of the design is a good way to do just that.
Figure 1: Functional Coverage Flow Diagram
Functional coverage is user-defined, mapping all functionality defined in the test plan to be tested to a cover point.