Until recently, the semiconductor industry religiously followed Moore's Law by doubling the number of transistors on a given die approximately every two years. This predictable growth allowed ecosystem partners to plan and deal with rising demands on tools, flows and methodologies. Then came the mobile revolution, which opened up new markets and further shifted the industry's focus to consumers. The diversified nature of this market posed many, often conflicting development challenges: How to speed time to market while building products rich in functionality? How to boost performance while keeping both power consumption and cost at modest levels? Wading through these questions contributed to a multifold increase in verification complexity.
What hasn't changed is that, for decades, the majority of the re-spins have been attributed to functional failures. Verification teams, in fact, have been in constant pursuit of first silicon success, it's just that the new challenges make it that much harder to achieve that goal. What's needed is a well defined process to achieve verification closure, one that brings predictability and organization, while accelerating the time-to-closure at reasonable cost. One key to achieving this is extracting useful information from the vast amounts of generated simulation data, and then using this information to drive prompt and informed decision making.
Any such verification platform must facilitate:
- objective representation of verification goals
- the efficient collection and merging of coverage
- trend analysis on progress with respect to test plan and overall goals
- coverage grading to eliminate redundant simulation cycles
- results analysis to jumpstart debug
- decrease in maintenance or upgrades, including of in-house automation
- methodical processes that lead to verification closure
Questa Verification Manager (QVM) is one potential means to address the above wish list. QVM-enabled flows have been successfully deployed in our turnkey engagements and have resulted in better controllability, predictability and communication of milestones with customers. This paper further summarizes our experience setting up QVM and how its capabilities are superior to many traditional automation flows developed in house.
Objective Representation Of Verification Goals
Traditionally, a directed verification flow involved developing a test plan followed by test cases, each of which would map back to one or more test points in the plan. With rising complexity came an embrace of constrained random verification. In this approach, the test bench is sophisticated and test generation is guided by a set of constraints. The progress of verification is measured using a set of coverage goals. Test plans didn't keep up with this evolution. Often, plans were written as they always had been, with the only change being addition of a new section describing the test bench. Accordingly, disconnect between planning and execution was a major challenge. Slight deviations from the plan often weren't accounted for when implementing the test bench. Changes in specifications further knocked the verification plan and environment out of sync. Despite the rise of reusability, there was no mechanism to import a part or complete test plan from IP to the SoC level, except by mentioning references. Progress was measured solely through coverage and didn't reflect the percentage of the test plan covered.
A QVM-enabled flow addresses all these issues by tightly coupling coverage with the test plan. We divided our planning into a verification strategy document covering 'how to verify' and a verification plan indicating 'what to verify.' For the latter, we followed the XLS template provided by QVM. The schema follows a treelike structure that cleanly segregates the sections to be covered, also providing clearly defined and tagged subsections. Further, an engineer can define the goals for each cover point with corresponding weight in the plan itself. Additional customization adds priority to each entry and associates it with the verification engineer's name. For SoC projects, importing section(s) or a complete IP-level plan enables efficient IP- to SoC-level reuse.
Moving to this flow significantly improved our verification execution. The priority feature helps define goals based on each project milestone. Annotating coverage to the verification plan allows for measuring overall progress more objectively at any point during the execution. Issues are highlighted promptly and with enough information to take preventive actions. For example, coverage holes can be filtered with the click of a button, giving a clear view of what is pending and an ability to confirm if such holes can be addressed in a given time.
Figure 1: Closed loop between verification plan and coverage collection
Collect And Merge Coverage
Coverage metrics make it possible to quantitatively qualify verification progress. Coverage can be represented as a function of code coverage, functional coverage and assertion coverage. Threshold limits for number of hits required to declare a bin as covered and assigned weights further help in measuring momentum. Using conventional flows, we often faced issues such as merging coverage generated using tools from different vendors, sprawling overall memory footprint and vast amounts of time consumed in the merging process. In addition, requirements that we merge part or complete coverage from a different database like an IP into SoC were especially challenging. QVM effectively addresses these issues. The flow we adopted ensures flexibility to merge coverage on the fly, or in post processing mode, quite efficiently reducing overall time to merge multiple databases. The flow also optimizes overall memory requirement. The strip and install feature merges coverage from different test benches at various hierarchical levels. 'Strip' removes required levels of hierarchy from instance and object names in coverage files, while the 'install' adds a defined hierarchical path to those instance and object names before merging.
'Where are we?' is the looming question in every project status meeting. The answer to this is usually verbose but often fails to provide a clear idea of progress towards the goals. Previously, to understand trends, we used highly manual methods, extracting data from merged coverage databases and mapping it to graphs. The process was time consuming and provided limited accuracy. In contrast, the automation enabled by QVM is highly accurate and efficient. Required trends are extracted on the fly while merging into a new trend UCDB that is optimized for memory. Various trends related to coverage progress, code stability, failure analysis and so on can be derived in the form of graphs for the whole project, each team member, each design block, each design instance or even each section of the test plan. This also enabled us to delete the older coverage database from our weekly regressions, as this was only maintained to extract information for trend analysis. The extracted data provides useful information for stakeholders to crosscheck the requirements of various milestones versus progress and decide on the course of action.
The main drawback of constrained random verification is the waste of redundant simulation cycles. Typically, once the environment is stable, random regressions are run to hit the desired cover points. Any change to the DUT would require rerunning these regressions and collecting coverage ensuring nothing else was broken. A lot of random simulations may not contribute to overall coverage, thus leading to wasted hardware resources and extended regression time. Coming up with a focused set of random tests ensuring maximum coverage was a challenge.
The ranking technology available in QVM overcomes this issue automatically. Once the regression is able to hit desired coverage numbers for a given milestone, the simulations can be ranked based on their contribution to overall coverage. Users can chose the 'Iterative' or 'Test associated' algorithm for directing the ranking process to be followed by the tool. The flow provides a list of tests that are contributing and the incremental share from each test, and also a list of non contributing tests. The contributing tests can be used to create a regression that helps in achieving desired coverage results with an optimum number of simulations on every DUT change. Grading helps reduce overhead associated with random simulation, thereby optimizing schedule and cost. The advantages are highly visible during the peak verification activities, when considerable time savings are perhaps most apparent.
Debug claims the maximum bandwidth of a verification engineer. Constrained random regressions add further complexity to this process. Engineers need to first sort out the failures before doing root cause analysis. Typically, post processing scripts are developed to do this sorting. The scripts help categorize and summarize the failures, though often not elegantly. Maintaining these scripts is an added task for the verification team.
The triage analysis feature of QVM addresses this concern as part of the flow without additional overhead. The summary report gives details for each error, warning and information generated in terms of how many tests are affected and at what time stamp. Many other configurable options allow users to collect and segregate information that can help to narrow down the issues. Additional performance data in terms of simulation and CPU time is available. All these reports can be viewed in a GUI or as transcripts for detailed analysis and boosting the debug process.
Automating The Verification Process: Focus On DUT Verification
The primary job of any verification team is to ensure that the design is an exact representation of the specification. To enable this, test plans, test benches and test cases are developed. The promise of automating some of the verification flow is the ability to accelerate execution and avoid human errors. Thus, significant bandwidth is spent to setup this flow for a new project, upgrade the flow for updates in tools, debug and fix issues found during execution and, still compromise on certain aspects.
The in-house flow was replaced by QVM's Verification Run Manager (VRM), thereby leveraging the expertise of the CAD teams from Mentor. QVM requires only modest setup time and the flow is ready on day one of the project. It also enabled us to integrate and reuse some of our existing scripts. Upgrades to the simulators are propagated seamlessly without any intervention from the verification team. By adopting this flow, our team was able to avoid spending time maintaining in-house flows, instead and utilizing that bandwidth to focus on verification. And QVM provides a rich set of features and cost-reduction benefits that were missing in our flows.
Figure 4: Summary of QVM flow
Verification usually is the long pole in the overall ASIC design cycle. Through the years, advances in test planning and in-house automation in verification technologies enabled engineers to effectively weed out corner cases and hidden bugs. However, these advances didn't scale. Accordingly, efforts to manage verification closure throughout the execution continued to run into challenges resulting in schedule delay, added cost and in some cases functional failures on silicon. A QVM-enabled flow enables verification teams to define an executable verification plan and track it using trend analysis. Additional features like results analysis give a jumpstart to debugging; coverage grading helps avoid redundancy from random simulations. With a relatively simple setup and easy user interface, transitioning to this flow is quite smooth. Adopting QVM enabled us to control schedule deviation, take preventive actions promptly and communicate effectively about the progress to remote customers on each milestone. We improved project planning using mining periodic snapshots collected from multiple past projects. And we saved money by efficiently utilizing hardware resources and engineers' bandwidth.
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