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INTRODUCTION
SVA ( SystemVerilog Assertions) is a powerful short-handed assertion language with many constructs; it is built as an integral part of SystemVerilog but with a specific syntax and sets of rules. Unlike a scoreboard that tends to focus on a model implementation that mimics the DUT, SVA addresses the requirements; that brings out a better understanding of the requirements, along with its weaknesses for lack of definitions. Over the years, I experienced the difficulties that engineers have in the thorough understanding of the SVA underlying model and why sometimes the assertions behave unexpectedly to the users' intent.
This article is a follow-up to the SVA Alternative for Complex Assertionsarticle published in the March 2018
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