As designs, especially System on Chip designs, have become more complex, the need for generated good automated stimulus across the verification spectrum has increased. Today, the need for verification reuse and automated stimulus is clearly seen from block to subsystem to SoC-level verification. The Accellera Portable Test and Stimulus Standard (PSS) language supports this need with a language for capturing test scenarios in such a way that they are reusable across verification levels (block, subsystem, and SoC) and across execution environment (simulation, emulation, and prototype), as illustrated in figure 1.
A language with such an ambitious scope must, of course, support a wide variety of applications and use models. This is