Verification Horizons Articles:
by Harry Foster, Siemens EDA
A verification crisis is upon us that will not be solved solely through improvements in verification methodologies and techniques. The solution requires a holistic and philosophical change in the way we approach design with a foundation based on bug prevention. Our proposed first step in implementing this change tightly integrates static analysis into the design process, resulting in a decrease in bug density, which has a positive impact on downstream processes and consequently reduces cost.
by Vidushi Goel, Siemens EDA
In PCIe® 6.0, the data rate has doubled from 32 GT/s to 64 GT/s. This technology is a cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data centers, artificial intelligence/machine learning, HPC accelerators, and data center applications like high-end SSDs, automotive, IoT, and military/aerospace, while also maintaining backward compatibility with all previous generations of PCIe. The entire protocol stack must be able to utilize the allocated bandwidth fully in compliance with the physical layer speed to deliver the maximum throughput.
by Om Prakash, Siemens EDA
In today’s modern era, there has been an increase in the relentless push for higher-speed data transfers along with the security of the data to be transferred. The need for protecting the confidentiality of data is increasing day by day. The need to process higher data bandwidth is catered with the increased speed of PCIe®. In contrast, data integrity is maintained by encrypting it with the introduction of the Integrity and Data Encryption (IDE) feature in PCIe. Data protection is critical with increasing applications of high data processing rates in Artificial Intelligence, Cloud computing, and servers. This protection is achieved by using some of the best-practiced algorithms in the industry to encrypt the data and maintain its integrity.
by Vishal Baskar, Siemens EDA
Increasing efficiency while debugging involves having access to the right tools, permissions, and the ability to use the debug tool to its fullest. We know how engineers spend their time debugging rather than verifying. Provide them with all the features of a debugging tool, and they would not have exited the tool while enjoying debugging. An average user spends their time looking at waveforms, looking for failing signals, and when they figure out a wrong value in the wave, they trace it and modify the source code. How do we ease this process?
by Avnita Pal and Sastry Puranapanda, Silicon Interfaces®
Fault Simulation needs to toggle every node with Stuck@0 and Stuck@1 faults. Running traditional fault simulation on hundreds of thousands or even millions of nodes can take days or weeks, even on large parallel computers. We can measure Failure in Time (FIT) for permanent and transient errors in a design. To measure diagnostic coverage (DC), we may need to run many fault cycles in the fault simulation. Even a small change could take days to validate. It should be possible to apply intelligence and learning algorithms to Standard fault Simulation and industry techniques to reduce simulation cycles.
by Ben Cohen, SystemVerilog Assertions Expert
Immediate assertions are typically used to verify that expressions are within their required bounds, such as no overreach of the value of a counter or an illegal condition such a write without an enable. The action block is typically used for debug to display more information as to the cause of the error. However, immediate assertions can also be used to modify testbench variables for use in monitors or in other assertions, or to change the course of a testbench flow. This article explains the immediate assertion modes, their restrictions, and it provides guidelines into their uses.