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Modern system-on-chip (SoC) designs contain a high level of complexity in the reset distribution and synchronization circuitry. Verifying that a design can be correctly reset under all modes of operation presents a significant challenge. In this article, we present the commonly occurring issues that are involved in reset tree verification and solutions to address them.
INTRODUCTION
Today’s SoC designs integrate many design IP blocks from various providers, each with their own implementation of reset. The reset architecture of a digital design can also be very complex. Designs have multiple sources of reset, such as power-on reset, hardware resets, debug resets, software resets, and watchdog timer reset. Errors in reset design can lead to
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