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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
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    • Pattern Resources

      • Start Here - Patterns Library Overview
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      • Verification Horizon - The Verification Academy Patterns Library
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Web Seminar: Clock-Domain Crossing Analyses and Verification - June 27th
      • Web Seminar: Accelerate Design-to-revenue in ASIC Developments - July 10th
      • Low Power Verification Forum
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • Stimulus Generation
      • All On-Demand Seminars

    • Recording Archive

      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • DAC & DVCon
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    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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    • Training

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  • Home /
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  • UVM - Universal Verification Methodology /
  • UVM Framework

UVM Framework

UVM Framework

UVM Framework is a combination of a class library and a code generator, delivered as part of the Questa® Verification Solution, that enables you to build a UVM testbench within an hour. Providing an architecture and reuse methodology, it allows verification teams, whether they are experienced or new to UVM, to assemble operational UVM testbenches, including industry-standard Questa VIP components, freeing the team to focus on verifying product features. The UVM testbenches developed with UVM Framework are also compatible with our Veloce® emulator.

UVM - Universal Verification Methodology

Featured Course - UVM Framework

UVMF - Series Introduction

UVMF Series Introduction Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you are introduced to the UVM Framework and the list of sessions that comprise this video course.

UVMF - Overview

UVMF Overview Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you will learn what the UVM Framework is, the functionality it provides, its testbench architecture, and available documentation and support.

Code Generation Introduction

Code Generation Session | Subject Matter Expert - Jonathan Craft | UVM Framework Course

In this session, you will learn why code generation can be a powerful tool and how to take advantage of it for the purposes of quickly producing a UVMF-based testbench.

Agents: Architecture and Operation

Agents: Architecture and Operation Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you will learn about components within a protocol agent and its associated bus functional models and the roles and responsibilities of these components including the abstraction level they operate at.

Interface Code Generation

Interface Code Generation Session | Subject Matter Expert - Jonathan Craft | UVM Framework Course

In this session, you will learn the steps needed to produce code for an UVMF Interface using the generator.

Environments: Architecture and Operation

Environments: Architecture and Operation Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you will learn the roles and responsibilities of an environment within a simulation.

Scoreboards and Predictors

Scoreboards and Predictors Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you will learn the roles and responsibilities of scoreboards and predictors within the UVMF, the scoreboards provided by UVMF and how they are configured.

Questa® VIP Integration

Questa VIP Integration Session | Subject Matter Expert - Dave Aerne | UVM Framework Course

In this session, you will learn how to integrate Questa® Verification IP within your UVMF testbench.

Environment Code Generation

Environment Code Generation Session | Subject Matter Expert - Jonathan Craft | UVM Framework Course

In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Environment and what parts of the generated output that you'll need to modify afterwards.

Testbench: Architecture and Operation

Testbench: Architecture and Operation Session | Subject Matter Expert - Bob Oden | UVM Framework Course

The UVMF testbench contains top level modules, top level sequence, top level environment, and top level configuration. In this session, you will learn about the architecture of a UVMF testbench and directory structure.

Bench Code Generation

Bench Code Generation Session | Subject Matter Expert - Jonathan Craft | UVM Framework Course

In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Bench and what parts of the generated output that you’ll need to modify afterwards.

Instantiating the DUT

Instantiating the DUT Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you will learn how to compile and instantiate a Verilog and VHDL DUT within a UVMF testbench.

Adding Tests and Sequences

Adding Tests and Sequences Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you will learn how to add sequences and test cases to a UVMF testbench using the example derived test and extended top level virtual sequence.

Sequence Categories

Sequence Categories Session | Subject Matter Expert - Bob Oden | UVM Framework Course

In this session, you will learn the roles and responsibilities of the sequence categories and that sequences within UVMF are divided into three categories: interface, environment, and testbench.

UVMF & Emulation

UVMF and Emulation Session | Subject Matter Expert - Michael Horn | UVM Framework Course

The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there.

Running Simulations

Running Simulations Session | Subject Matter Expert - Jonathan Craft | UVM Framework Course

In this session, you will learn how to run individual UVMF simulations in both batch and debug mode as well as how to configure and run a regression test suite using the Questa® Verification Run Manager.

Featured Sessions

Get a Head Start on the New UVM Standard

DAC 2016 | Get a Head Start on the New UVM Standard

This session will discuss the new version of UVM coming from the IEEE, the changes and how they'll impact current UVM users. We'll also fill you in on the latest happenings in the UVM committee and introduce you to the UVM Framework.

Off and Running with UVM

DAC 2015 | Standards & FPGA Tuesday | Off and Running with UVM

This session will show you how to be more effective in deploying UVM in your verification flow.

Featured Resources

Slaying the UVM Reuse Dragon

Authors:
  • Mike Baird - WHDL
  • Bob Oden - Mentor Graphics

Abstract:

With larger and more complex designs the gap between design and verification has grown larger. Because of this the reuse of the testbench both in new projects and within the same project has become very desirable. One of the "promises" of UVM is achieving such reuse. However, in reality, UVM reuse has been limited. This paper identifies the issues that affect UVM reuse and strategies for achieving reuse. A UVM reuse methodology will be presented that provides reuse of components from one testbench to another and within the same testbench from block to chip level.

View Poster

  Slaying the UVM Reuse Dragon - Issues and Strategies for Achieving UVM

A Simplified and Reusable UVM Config DB Methodology

Author:
  • Bob Oden - Mentor Graphics

Motivation:

  • Provide a mechanism for sharing resources within a simulation that provides features needed by architects and simplicity needed by test writers.
  • Architects need a mechanism that can allow resource access by hierarchy and general scope.
  • Test writers need access to simulation resources while treating environment as a black box.

View Presentation

  View Full Poster in PDF

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