Functional Verification Using Siemens Questa Simulation Technologies
Working at the leading edge of AI Computing, with Chiplet architectures, advanced protocol and memory interfaces, it is essential that our IPs, DUTs, and functional Design Verification teams continue to scale up along with our product line and company. In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.
Full-access members only
Register your account to view Functional Verification Using Siemens Questa Simulation Technologies
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.