Did You Know QuestaSim Supports VHDL-2019?
In this webinar, we will explore the VHDL-2019 supported features in QuestaSim such as; enhancing your VHDL testbench, accessing the host environment, assertion reporting, view modes for design configuration optimization and more.
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Session Registration
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Session Overview
VHDL-2019 introduces a set of powerful features and enhancements that aim to simplify design processes, improve code readability, and provide better support for advanced design methodologies. In this webinar, we will explore the VHDL-2019 supported features in QuestaSim. This includes and not limited to:
- String representation of values of composite types: Predefined implicit operation to_string() and predefined attribute 'IMAGE now support composite types. They return a string representation for composite type values.
- Garbage collection: Efficiently managing memory by automatically deallocating unused objects, enhancing resource utilization.
- Update ENV package: ENV package is updated with new VHDL 2019 type definitions and APIs. The following APIs are supported:
- Date and Time API: Date and time supported along with to_string() function for time records. Date and time do not support microseconds precision (computes it as 0)
- GETENV function: Provides a VHDL interface to the host environment
- APIs for Assertions: APIs to collect information on report and assert statements. Information is collected per severity level (FAILURE, ERROR, WARNING, or NOTE) and can be enabled and disabled per severity level.
- Report Calling Path and Current File: Reports call path information for the current stack frame.
- Allow empty records: Allow more flexibility in code writing. For example, initialize a record with an empty value of the type or subtype.
- Conditional Expressions: Conditional declaration and conditional expressions are supported using when - else clause.
- 2019 syntax: Component declaration supports "end" without the need for mentioning "component" keyword. Also, optional Trailing Semicolons on Interface Lists.
- View Modes: The Capability to assign specific modes (input/output/inout) to each individual member within records. This advancement allows for much greater flexibility and precision in designs.
What You Will Learn
- How to use VHDL-2019 features to enhance your VHDL testbench
- How VHDL testbench can access host environment
- How to get assertions report from VHDL testbench
- How to get the current date and time in your VHDL testbench
- How to apply view modes to manipulate different design configurations
Who Should Attend
- Design and Verification Engineers
Products Covered
- QuestaSim and Visualizer
