Solving the Semiconductor Verification Crisis: From Problem to Productivity
In this webinar, you will more about the challenges that are currently being faced by the digital design and verification industry and the steps we can take to mitigate some of these challenges.
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Session Registration
https://event.on24.com/wcc/r/4937687/C2DBD22A37D85355E3777994F0AC4EA5
Date & Time
- Wednesday, May 21st
- 08:00 AM | US/Pacific
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Session Overview
The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures.
This challenge is compounded by demands for Enhanced security, Reduced power consumption, Improved reliability, Greater sustainability and Talent shortage mitigation. Traditional verification methods, including constrained-random and formal verification, are proving inadequate for modern semiconductor design complexities.
Siemens has developed a transformative solution through Connected Platforms, Data-driven approach and AI Integration to address challenges faced by Cross-design-domain dependencies, Workforce limitations, Verification efficiency, Quality assurance. This solution transforms traditional approaches into a proactive, intelligent, and self-optimizing system.
It meets modern design complexities while ensuring efficient resource utilization and robust verification processes. Through this innovation, Siemens addresses the industry's pressing need for advanced verification solutions in an increasingly complex design environment.
What You Will Learn
- Challenges that are currently being faced by the digital design and verification industry and the steps we can take to mitigate some of these challenges
Who Should Attend
- Digital Design Engineers
- Verification Engineers
Products Covered
- Questa Simulation
- Static & Formal
- Verification IQ
- Avery Verification IP