Enhancing Defect Coverage in Design for Testability (DFT) with Functional Fault Grading
In this webinar, we will explore how functional fault grading enhances defect coverage. Attendees will learn the key advantages of integrating functional fault grading into DFT processes, specifically addressing faults untestable by scan tests.
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Session Registration
https://event.on24.com/wcc/r/4942797/08D07F230AD1238395638CAF18EB5C11
Date & Time
- Wednesday, May 7th
- 08:00 AM | US/Pacific
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Session Overview
In today’s complex semiconductor designs, ensuring robust and efficient testing is crucial for reliable and safe product deployment.
Developers of high-performance and safety-critical ICs face market pressure to achieve zero defects per million (DPPM).
Functional fault grading is essential for optimizing Design for Testability (DFT), enhancing defect coverage to meet coverage goals.
In this webinar, we will explore how functional fault grading enhances defect coverage. Attendees will learn the key advantages of integrating functional fault grading into DFT processes, specifically addressing faults untestable by scan tests.
Our expert speakers will demonstrate how these benefits lead to higher reliability and reduced time-to-market. Whether you are a design engineer or test engineer, this webinar will offer valuable insights into leveraging functional fault grading for robust and reliable system designs.
What You Will Learn
- Some of the challenges Semiconductor developers face in DFT
- About Siemen’s integrated functional fault grading solution with Tessent TestKompress
- Areas of the design to use fault grading
- How fault grading can enhance defect coverage and help semi developer approach zero DPPM
Who Should Attend
- Test Engineers
- Design Engineers
- Verification Engineers
Products Covered
- KaleidoScope DFT