AI Assisted FPU Verification Using Questa One SFV
One of the key components of the AI revolution is Floating Point Hardware design. Design targeting AI requires at times fast computing with low precision and at times very high precision in its calculations.
In this webinar we show how Questa One AI assisted tools for Static Formal, help to generate full formal verification checkers for user defined functionality including floating-point operations.
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Session Registration
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Session Overview
The AI revolution is taking place in the last few years, fueling a great deal of High-Performance Computing (HPC) designs to implement such an immense demand for computing.
One of the key components of the AI revolution is Floating-Point Hardware design. Designs targeting AI requires at times fast computing with low precision and at times very high precision in its calculations.
Verification of floating-point operations including Matrix multiplications, conversions, vector operations all considering an even larger number of datatypes, being defined in the last few years such FP8 and FP4, MX vectors and more.
This verification requires exhaustiveness and the ability to cover different data types, different rounding modes and mixed result – operand types.
In this webinar we show how Questa One AI assisted tools for Static Formal, helps to generate full formal verification checkers for user defined functionality including floating-point operations.
What You Will Learn
- How to get help of AI assisted tools such as Property Assist to develop comprehensive Formal FPU operations verification
Who Should Attend
- Design and Verification engineers who are required to exhaustively test floating-point operations, data type conversion, mixed data type operations
Products Covered
- Questa One SFV
