Released on June 5th, 2020
Chris Spear, Principle Instructor, presents a detailed description of the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. SystemVerilog has many dynamic data types, and you will learn which ones to choose for scoreboards, sparse memories, hash arrays, and more. As a result, your testbench code will be easier to understand and reuse, run faster, and consume less memory. These array types are part of the building blocks for verification methodologies including UVM.
What You Will Learn:
- How to apply the string type, including formatting and parsing
- The differences between vectors and arrays
- When to choose a fixed size array and a dynamic array
- Modeling scoreboards with queues
- Modeling large memories with associative arrays
- A simple guide to choosing between these array types
- Built-in SystemVerilog methods to search sort, and reduce arrays
