Released on August 13th, 2020
Modern SoCs comprises of many design blocks with different functionalities and need different reset controls (global/local) for each blocks. Thus these blocks have multiple asynchronous resets. Asynchronous resets help these blocks/systems to clear faults and recover to a good state. Having local control to resets initialize only faulty logic and other logic remains functional. Interaction between multiple asynchronous resets may cause chip failure due to RDC issues introducing meta-stability in the design.
This web seminar will give you an overview of Reset Domain Crossing problem and methods to address it. Will also talk about Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR. It will cover the abstract flow support, we have for RDC analysis, which is quite useful for big Subsystems and SoC designs in today’s era.
What You Will Learn:
- Basics of Reset Domain Crossing issues
- How to catch them and fix early in the design cycle by either using existing reset architecture or by adding appropriate isolation/synchronizer
- Learn Questa RDC solution and methodology to catch and address these issues