Released on January 25th, 2022.
Have you ever had RTL code that passes simulation but still fails due to things like unreachable code, out-of-range violations, or incorrect order of execution? Have you ever dealt with a multi-clock design that had glitch or reconvergence issues in silicon that took weeks to root cause? See how the correct verification tools can resolve these types of problems before you signoff on your design.
Simulation and Static Timing Analysis are great for first pass verification, but they are not sufficient for ASIC signoff level verification. Repeated rewriting and recompiling code (a.k.a. "burn and pray") for FPGAs is an extremely slow and error prone way to insure your code is ready for release. To reach signoff/release level verification, other methodologies must be implemented that go beyond the tried and true techniques.
In this technical session, we focus on:
- Why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block
- What metastability is and how it will affect silicon bring-up
- How addressing these points during the design process is critical to achieving tight schedules with limited resources
What You Will Learn:
- How linting can improve RTL code
- How to handle crossing clock domains in a multi-clock domain design
Who Should Attend:
- ASIC, FPGA and IP Design and Verification Engineers & Managers and those interested in achieving higher quality RTL code and avoiding issues with multi-clock domain designs