Released on July 27th, 2021.
Systematic design errors introduced by automated design refinement tools, such as synthesis, can be hard to detect, not to mention damaging if they make it into the final device. Formal equivalence checking has been used for ASIC design flows for many years. As FPGAs become bigger, critical system components exhaustively verifying the functional equivalence of register transfer level (RTL) code to synthesized netlists and the final placed-and-routed FPGA designs is mandatory. FPGA implementation verification can accelerate design flow, reduce testing in the lab, enable aggressive optimization usage, and dramatically reduce post-production risks.
The session will:
- outline the differences between formal verification and simulation in the context of equivalence checking
- define the verification challenges for sequential optimizations
- discuss the advantages of a step netlist verification approach and related applications
- present further related tasks that can be targeted using an equivalence checking verification flow
What You Will Learn:
- The need of equivalence checking for FPGAs
- Methodologies to apply equivalence checking
- The advantages and challenges of stepwise netlist verification
Who Should Attend:
- Design & Verification Engineers & Managers