Release date: July 19th, 2023.
RISC-V is gaining immense traction in the embedded space, with more and more application cores emerging as well. This broad range of available cores coupled with the ability to include custom extensions opens unprecedented innovation opportunities in the SoC domain. However, verification of those highly parameterized core instances, including their custom extensions, remains a time-consuming challenge – keep in mind that state-of-the-art processor DV was mostly practiced by a few big players in the market prior to RISC-V.
In this session, we present an automated, customer proven flow from ISA level specifications of custom extensions to their exhaustive formal verification and demonstrate results on popular open-source cores.
What You Will Learn:
- A 10,000-foot view of RISC-V and its customization opportunities
- The role of formal in state-of-the-art processor DV
- Application results of Questa OneSpin (QOS) Processor Core Verification
- How to generate verification of your custom instructions and registers
- The QOS Processor Core Verification workflow and demo
Who Should Attend:
- Engineers considering RISC-V adoption in a future project
- RISC-V core suppliers
- RISC-V core end-users with customization needs
What/Which Product(s) are Covered:
- QOS Processor Core Verification
