Released on June 2nd, 2020
Intuitive and easy to use, Visualizer Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs.
Find problems in your UVM testbench faster using Visualizer Debug Environment, a high-performance, high-capacity debugger. UVM testbenches can be intuitively debugged in either interactive simulation or post simulation. You will see UVM Objects, UVM Components, Class Instances, transactions and more. Visualizer provides UVM visibility in all windows including the wave window, the source code window, the watch window. Breakpoints can be set, including conditional and instance based.
Learn how you can save time and improve UVM debug techniques.
This session will take you through UVM Debug tips and tricks in both Post simulation and Live simulation.