Released on May 21st, 2020
A significant evolution is underway in SoC verification and validation, especially in the areas of AI/ML, 5G and Automotive. The complexity of SoC designs has resulted in the need to perform both comprehensive verification as well as system-level validation very early in the design cycle, often before stable register-transfer level (RTL) code is available for the entire design. This same complexity has also created the need for extensive internal visibility into the design to understand subtle problems that can occur during silicon bring-up. Hardware emulation has sufficient execution speed, full visibility capabilities and ease-of-use in model creation and model updates to span the entire range of needs throughout the life of the design development process.
What You Will Learn:
- How AI/ML, 5G, networking and ADAS designs are affecting verification and validation
- How Veloce Strato’s proven hardware emulation architecture addresses these challenges
- How Veloce VirtuaLAB solutions and Veloce Apps address unique verification challenges
