The benefits that UVM provides in specifying modular reusable testbenches have been well documented. Regardless of these benefits, however, the need to adequately model functional coverage, and efficiently create stimuli to reach your coverage goals, remains. The use of UVM sequences allows encapsulation of constrained-random stimulus that can be reused, and virtual sequences allow composition to orchestrate stimuli on multiple interfaces to your DUT. Unfortunately, the use of procedural constraint-based coding for stimulus has two distinct disadvantages. First, since constraints and coverage goals are distinct language features in SystemVerilog, they must be coded separately and there’s no easy way to map one to the other. Second, the reliance on constrained-random stimulus means that specific cases are likely to be repeated, leading to an asymptotic approach to your coverage goals.
Raising the level of stimulus abstraction allows you to specify your stimulus once and integrate the coverage model directly in the specification. This abstract stimulus can easily be mapped to UVM sequences at multiple levels of abstraction as well as to software for execution on a processor model, greatly enhancing the reusability of the stimulus.
This Verification Cookbook seminar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow.