Component level reuse across projects and environment level reuse from block to top remains elusive to many verification teams after many environment iterations. A well defined and proven reuse methodology ensures reuse becomes a reality and not just a myth. Simple, efficient and effective reuse takes planning at the architectural level and discipline at the implementation level. The reuse methodology outlined in this presentation has been proven on multiple projects at multiple companies. It has even been used to achieve subsystem environment reuse across multiple companies working on the same SOC design. Many companies have used this methodology to establish a company wide verification library for both FPGA and ASIC verification. This session will outline key characteristics of a reuse verification library and will outline a proven reuse methodology.
