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2028 Results
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Breaking the Bottleneck: Overcoming the Verification Productivity Gap 2.0
Resource (Paper (.PDF)) - Jan 31, 2025 by Harry Foster
By integrating AI-driven technologies, we can automate workflows, derive actionable insights and significantly enhance precision in identifying and resolving bottlenecks. This approach will address cross-design-domain interdependencies, alleviate workforce strain and ensure more robust, efficient verification.
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Breaking the Bottleneck: Overcoming the Verification Productivity Gap 2.0
Paper - Jan 31, 2025 by Harry Foster
The semiconductor industry is confronting the Verification Productivity Gap 2.0, characterized by the unique complexities and challenges of the latest semiconductor design technologies. Siemens envisions a transformative solution through connected, data-driven and scalable verification platforms designed to accelerate processes and optimize resource allocation.
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Next-Gen Memory Unlocked: HBM4 and LPDDR6 Verification for High-Performance Computing
Resource (Slides (.PDF)) - Jan 30, 2025 by Kamlesh Mulchandani
In this session, discover how Siemens’ Avery Verification IP for HBM4 and LPDDR6 provides a scalable and customizable solution for rigorous protocol compliance and performance testing. Learn how our leading users leverage this VIP to verify their memory controller IP and subsystems, ensuring reliability and readiness for next-generation applications. Guest Speaker: Nidish Kamath from Rambus spoke about Rambus's HBM4 memory controller and the partnership with Avery memory VIP.
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Bridging SoC HW/SW: Co-simulation Challenges and Solutions for X86, ARM, RISC-V Based SoC Teams
Resource (Slides (.PDF)) - Jan 30, 2025 by Chris Browy
The Avery VIP team have created solutions in this space that can mix abstraction levels and software as stimulus for our SoC subsystem testbenches. We'll demonstrate how you can benefit from fast, productive verification, while in the simulation phase of your project, with our available Virtual In-Circuit Simulation VIP solutions.
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Accelerating Innovation: PCIe Gen7 Verification for High-Speed Design
Resource (Slides (.PDF)) - Jan 30, 2025 by Zhihong Zeng
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks. Discover how this native SystemVerilog/UVM VIP enables rigorous testing of performance, power efficiency, and scalability, ensuring designs meet demands of next-generation PCIe applications. Guest Speaker: Ganesh Venkatakrishnan from Scaleflux presented his experience with the Avery PCIe VIP.
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Breaking Barriers: Ethernet 1.6T, UALink, and UEC Verification for Next-Gen Connectivity
Resource (Slides (.PDF)) - Jan 30, 2025 by Pankaj Goel - Siemens EDA
This session introduces Avery Verification IP for Ethernet 1.6T, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.
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Mastering UCIe 2.0 Verification: Ensuring Seamless Chiplet Integration
Resource (Slides (.PDF)) - Jan 30, 2025 by Luis Rodriguez
This session will focus on the Siemens Avery UCIe Verification IP and the new UCIe2.0 features. Discover its capabilities in dynamic environment creation, including generating complex SiP topologies, portable traffic generation, error injection, and debugging all within a native SystemVerilog/UVM framework.
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An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262
Resource (Slides (.PDF)) - Jan 29, 2025 by Jyothy M Jaganathan
Requirements gathering, tracking, safety analysis, and validation all play a critical role; where collaboration between cross-functional teams of safety managers, hardware, software, and verification engineers is needed to guarantee that the chip meets the specified safety standards.
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An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262
Webinar - Jan 29, 2025 by Jyothy M Jaganathan
In this webinar, you will learn more about Siemens EDA functional safety concepts and tool flow. In addition, we will walk you through our closed-loop solution; from requirements gathering, FMEDA, safety analysis, fault injection and back to merging the results to generate the work products necessary for certification.
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Explore How to Protect Against Data Corruption with Formal Security Verification
Resource (Slides (.PDF)) - Jan 22, 2025 by Keerthi Devraj
In this webinar, you will learn about the importance of hardware security including; why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems and the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.
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Explore How to Protect Against Data Corruption with Formal Security Verification
Webinar - Jan 22, 2025 by Keerthi Devraj
In this webinar, you will learn about the importance of hardware security including; why robust hardware security is fundamental to all security applications, especially as hardware forms the backbone of critical systems and the implications of hardware breaches, which can lead to severe financial, reputational, and operational consequences.
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Unlocking the Power of QuestaSim and Visualizer Integration
Resource (Slides (.PDF)) - Jan 15, 2025 by Justin Royse
In this webinar, you will learn how you can get faster simulation runs, smaller simulation databases. We will also cover qrun which simplifies your scripting environment by bringing together compilation, optimization and elaboration into a single command and fewer switches. Then we will cover how you can get better coverage performance using our Next-Gen Coverage engine.
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Unlocking the Power of QuestaSim and Visualizer Integration
Webinar - Jan 15, 2025 by Justin Royse
In this webinar, you will learn how you can get faster simulation runs, smaller simulation databases. We will also cover qrun which simplifies your scripting environment by bringing together compilation, optimization and elaboration into a single command and fewer switches. Then we will cover how you can get better coverage performance using our Next-Gen Coverage engine.
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Functional Verification of Digital Logic
Track - Jan 10, 2025 by Harry Foster
Dive into the world of functional verification with our advanced master’s-level course, developed in collaboration with North Carolina State University. This comprehensive program covers all essential aspects of creating sophisticated constrained-random, coverage-driven testbenches using SystemVerilog and UVM.
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Verification Process Overview
Session - Jan 10, 2025 by Harry Foster
This session, with five lessons shown in the tabs below, covers the Verification Process: where to start, what needs to be done, and when verification is complete. Learn about directed testing, constrained-random stimulus, and coverage metrics. Explore testbench tasks, component roles, and reuse strategies. Understand UVM test flow, from selection to completion. By the end, you’ll master effective verification strategies.
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Introduction to Functional Verification
Lesson - Jan 10, 2025 by Bob Oden
You will learn about the Verification Process, addressing three key questions. First, where to start? Even verifying a small design can be daunting. Starting right is crucial as it saves time and minimizes bug escapes. Second, what needs to be done? Each design has unique features to verify. Understanding required tasks is vital for planning, managing, and completing verification. Lastly, when is verification done? This common question arises as we near a project’s end.
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Introduction to Functional Verification
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn about the Verification Process, addressing three key questions. First, where to start? Even verifying a small design can be daunting. Starting right is crucial as it saves time and minimizes bug escapes. Second, what needs to be done? Each design has unique features to verify. Understanding required tasks is vital for planning, managing, and completing verification. Lastly, when is verification done? This common question arises as we near a project’s end.
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Understanding the Two Main Testing Approaches
Lesson - Jan 10, 2025 by Harry Foster
You will learn about directed testing and constrained-random stimulus, the two main testing strategies. We’ll discuss where to apply each strategy and how to measure testing completeness using coverage metrics. By the end of this lesson, you’ll have a solid understanding of how to effectively apply these strategies in your verification process.
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Understanding the Two Main Testing Approaches
Resource (Slides (.PDF)) - Jan 10, 2025 by Harry Foster
You will learn about directed testing and constrained-random stimulus, the two main testing strategies. We’ll discuss where to apply each strategy and how to measure testing completeness using coverage metrics. By the end of this lesson, you’ll have a solid understanding of how to effectively apply these strategies in your verification process.
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What is a Reusable Testbench?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn about testbench tasks, component roles, and customization for varied applications. You will also learn how to reuse components across projects, enabling efficient 'horizontal reuse'.
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What is a Reusable Testbench?
Resource (Slides (.PDF)) - Jan 10, 2025 by Tom Fitzpatrick
You will learn about testbench tasks, component roles, and customization for varied applications. You will also learn how to reuse components across projects, enabling efficient 'horizontal reuse'.
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How Can I Reuse Testbench Components?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn how to build and customize reusable testbench components. Discover 'vertical reuse' from block level to system level in your project.
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How Can I Reuse Testbench Components?
Resource (Slides (.PDF)) - Jan 10, 2025 by Tom Fitzpatrick
You will learn how to build and customize reusable testbench components. Discover 'vertical reuse' from block level to system level in your project.
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UVM Test Flow
Lesson - Jan 10, 2025 by Bob Oden
You will learn the flow of a UVM test: selecting, starting, understanding stages, ending, and the roles of testbench components.
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UVM Test Flow
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn the flow of a UVM test: selecting, starting, understanding stages, ending, and the roles of testbench components.