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Breaking Silos: Creating Synergistic Flows for Next-Gen Verification
Resource (Slides (.PDF)) - Oct 08, 2025 by Kirolos Magdy
In this webinar, you will learn strategies to eliminate workflow bottlenecks and create seamless collaboration between design and verification teams and how to architect verification environments where tools, processes, and teams work in perfect harmony.
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Interchange Format Standard in Hierarchical CDC and RDC Analysis
Resource (Verification Horizons Blog) - Oct 06, 2025 by Farhad Ahmed
For large designs with numerous asynchronous clocks and resets, there is a growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way. This allows parallelization of sub-block and noiseless analysis and helps reduce SoC runtime and speed closure of CDC and RDC issues at the SoC level.
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Beyond Traditional Testing: Integrating Design Verification and DFT for Zero-Defect Goals
Resource (Paper (.PDF)) - Oct 06, 2025 by Jyothy M Jaganathan
Fault grading is a critical component of DFT as it directly measures test quality through fault coverage, identifies gaps in test patterns, and guides improvements in scan architecture and logic design.
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Beyond Traditional Testing: Integrating Design Verification and DFT for Zero-Defect Goals
Paper - Oct 06, 2025 by Jyothy M Jaganathan
Hard-to-detect faults in high-stakes applications such as automotive, data center, and high-performance computing create a critical coverage gap that cannot be easily addressed through conventional structural testing alone, modifying existing DFT architectures to capture remaining faults typically involves substantial costs, increased silicon area, and performance impacts. This paper presents a closely integrated solution combining functional fault grading with traditional testing methods.
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Did You Know QuestaSim Supports VHDL-2019?
Resource (Slides (.PDF)) - Oct 01, 2025 by Abdelrahman Tharwat
In this webinar, we will explore the VHDL-2019 supported features in QuestaSim.
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Did You Know QuestaSim Supports VHDL-2019?
Webinar - Oct 01, 2025 by Abdelrahman Tharwat
In this webinar, we will explore the VHDL-2019 supported features in QuestaSim such as; enhancing your VHDL testbench, accessing the host environment, assertion reporting, view modes for design configuration optimization and more.
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Standardization of HDMs for Hierarchical CDC and RDC Analysis
Paper - Oct 01, 2025 by Farhad Ahmed
Currently HDMs must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the source of the generated model.
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Standardization of HDMs for Hierarchical CDC and RDC Analysis
Resource (Paper (.PDF)) - Oct 01, 2025 by Farhad Ahmed
Currently HDMs must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization.
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From Manageability to 3.0: Unlocking the Future with UCIe Verification
Resource (Verification Horizons Blog) - Sep 26, 2025 by Ujjwal Negi
The semiconductor industry is steadily moving toward multi-die integration, where chiplets from different sources are combined within a single package (known as a system in package or SiP) to deliver higher performance, scalability, and efficiency. The Universal Chiplet Interconnect Express (UCIe) standard is the backbone of this movement, offering a high-bandwidth, low-latency interconnect that enables heterogeneous chiplets to operate as one system.
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Pushing Boundaries: Smarter Verification for UCIe Multi-die Systems
Resource (Verification Horizons Blog) - Sep 18, 2025 by Ujjwal Negi
The semiconductor industry is at a turning point. As demand for higher performance and energy efficiency continues to grow, chipmakers are moving beyond monolithic SoCs and embracing multi-die architectures. By integrating multiple dies into a single package, designers can unlock new levels of scalability, flexibility, and cost efficiency.
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From Novice to Expert: Your Tutorial Roadmap at DVCon Europe 2025
Resource (Verification Horizons Blog) - Sep 17, 2025 by Joe Hupcey
In support of Verification Academy’s educational mission, Siemens is either directly sponsoring or contributing to the following five tutorials at the upcoming DVCon Europe 2025 on Tuesday, October 14th.
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No Reset? No Worries! Smarter Ways to Tackle RDCs to NRRs
Resource (Verification Horizons Blog) - Sep 16, 2025 by Reetika
As system-on-chip (SoC) designs continue to evolve, they’re not just expanding in size—they’re growing in complexity. Among the many challenges this evolution brings, one of the most subtle yet critical is the handling of resets. Modern architectures often juggle multiple asynchronous reset sources along with sequential elements, such as non-resettable registers (NRRs), which operate without dedicated reset pins.
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Class is Back in Session this October: Verification Academy’s Cutting-edge Weekly Webinar Series
Resource (Verification Horizons Blog) - Sep 16, 2025 by Joe Hupcey
Verification Academy’s fall semester starts this October with the following series of weekly deep dive webinars.
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Functional Verification Insights: A Conversation with Abhi Kolpekwar
Resource (Verification Horizons Blog) - Sep 15, 2025 by Harry Foster
Over the years, I’ve had the privilege of sharing industry data and analysis through the Siemens EDA & Wilson Research Group Functional Verification Studies . Those findings help us understand the challenges our industry faces—rising complexity, resource pressures, and declining first-silicon success rates.
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Automating Clock-Domain Crossing Verification for DO-254 (and Other Safety-Critical) Designs
Paper - Sep 10, 2025 by Kurt Takara
DO-254 methodologies must ensure that a device is going to behave as specified, and that everything possible is done to catch bugs before the device will be operating in flight. DO-254 projects should use an automated solution such as Questa™ CDC designed specifically for CDC verification to bridge the knowledge gap between design and verification teams, and to ensure comprehensive prevention of this problem.
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Automating Clock-Domain Crossing Verification for DO-254 (and Other Safety-Critical) Designs
Resource (Paper (.PDF)) - Sep 10, 2025 by Kurt Takara
Metastability is a serious problem in safety-critical designs in that it frequently causes chips to exhibit intermittent failures.
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The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.
Resource (Verification Horizons Blog) - Sep 08, 2025 by Rich Edelman
The grapes have returned – this weekend was “harvest” time. Jelly everywhere. A lot like this year here at Siemens. Lots of activity. New products. Announcements. Products everywhere. Jelly everywhere.
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Why First-Silicon Success Is Getting Harder for System Companies
Resource (Verification Horizons Blog) - Sep 03, 2025 by Harry Foster
Everyone wants their own chip. Few are hitting first-silicon success. That’s the paradox shaping today’s semiconductor landscape. In the 2024 Siemens EDA / Wilson Research Group Functional Verification Study , which I authored, we found that only 14% of ASIC/SoC projects achieved first-silicon success — the lowest figure in more than twenty years of tracking this data.
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Siemens at DVCon India 2025: Driving the Future of Design and Verification
Resource (Verification Horizons Blog) - Aug 26, 2025 by Dennis Brophy
DVCon India 2025 , taking place on September 10–11 at the Radisson Blu, Marathahalli, Bangaluru , will mark a special milestone—its 10th anniversary . Over the past decade, DVCon India has grown into one of the region’s most influential conferences for design and verification professionals. Siemens will be prominently featured across vision talks, technical papers, posters, and workshops, showcasing its leadership in AI-driven EDA, hardware-assisted verification, and formal methodologies.
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Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching!
Resource (Verification Horizons Blog) - Aug 25, 2025 by Dave Rich
The DVCon U.S. 2026 Call for Papers deadline is Sunday, September 7th at 11:59 PM . Don’t miss your chance to share your expertise and help shape the future of design and verification.
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SystemVerilog Transactions, UVM and C: Correlation in a Functional Verification Environment
Paper - Aug 20, 2025 by Rich Edelman
Transaction level modeling and transaction level debug have been in use for years in SystemVerilog and Verilog simulation and verification, but not as available in VHDL, perhaps not used in GLS simulation and C testbenches, and taking new forms in system level modeling. This paper re-introduces and refreshes transaction recording and debug and suggests how each abstraction level can be used productively with worked examples runnable by the reader.
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SystemVerilog Transactions, UVM and C: Correlation in a Functional Verification Environment
Resource (Paper (.PDF)) - Aug 20, 2025 by Rich Edelman
This paper re-introduces and refreshes transaction recording and debug and suggests how each abstraction level can be used productively with worked examples runnable by the reader.
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SystemVerilog Transactions, UVM and C: Correlation in a Functional Verification Environment
Resource (Slides (.PDF)) - Aug 20, 2025 by Rich Edelman
This paper will review the various APIs and methods for transaction recording and demonstrate the concepts using an example. That example can be reused in reader code and is open source.
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Verifying the Evolving UCIe Landscape: A 3.0-Aware Architecture for Manageability and Beyond
Resource (Paper (.PDF)) - Aug 13, 2025 by Ujjwal Negi
This paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework.
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Accelerating UCIe Multi-die Verification with a Scalable, Smart Framework
Resource (Paper (.PDF)) - Aug 13, 2025 by Ujjwal Negi
Multi-die architecture introduces layers of verification complexity along with protocol-level challenges. Questa One Avery VIP for UCIe provides a protocol-aware, layered verification framework that scales from block-level validation to full system-level testing. Its automation capabilities enable faster set up and targeted testing across diverse DUT configurations. Integrated debugging tools provide high observability and faster root-cause analysis.