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Part 6: FPGA Language and Library Trends

Resource (Verification Horizons Blog) - Nov 21, 2022 by Harry Foster

In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.
Functional Verification Study - 2022

Webinar - Nov 16, 2022 by Harry Foster

In this session, Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
Part 5: FPGA Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Nov 13, 2022 by Harry Foster

In this blog I present verification techniques and technologies adoption trends, as identified by the 2020 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was about seven years ago in terms of pre-lab verification maturity—and it is catching up quickly. A question you might ask is, “What is driving this trend?”
Part 4: FPGA Verification Effort Trends (Continued)

Resource (Verification Horizons Blog) - Nov 06, 2022 by Harry Foster

In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time. Verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in fig. 4-1. In 2022, design engineers spent on average 58 percent of their time involved in design activities and 42 percent of their time in verification.
Questa Design Solutions as a Sleep Aid

Webinar - Nov 02, 2022 by Vinayak Desai

In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
Questa Design Solutions as a Sleep Aid

Resource (Slides (.PDF)) - Nov 02, 2022 by Vinayak Desai

In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
Part 3: FPGA Verification Effort Trends

Resource (Verification Horizons Blog) - Oct 30, 2022 by Harry Foster

In this blog I focus on FPGA verification effort trends. Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…” In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.
ISO 26262…the Tale of Transient and Permanent Faults

Resource (Verification Horizons Blog) - Oct 27, 2022 by Jacob Wiltgen

Are you designing to the ISO 26262 standard and trying to decide if your design is safe from random hardware faults? If so, are you trying to figure out those annoying safety metrics (PMHF, SPFM and LFM)? If so, you are also undoubtedly weighing both transient and permanent faults.
CDC and RDC Assist: Applying machine learning to accelerate CDC analysis

Resource (Slides (.PDF)) - Oct 25, 2022 by Atul Sharma

In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis

Webinar - Oct 25, 2022 by Atul Sharma

In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
Industry Data and Surveys

Track - Oct 24, 2022 by Harry Foster

Every two years, Siemens EDA commissions Wilson Research Group to conduct a broad, vendor-independent survey of design verification practices around the world. Results of the functional verification study demonstrate an ongoing convergence of design and verification practices toward a common methodology.
Formal and the Next Normal

Webinar - Oct 19, 2022 by Joe Hupcey

In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.
Dig a Pool of Specialized SystemVerilog Classes

Resource (Verification Horizons Blog) - Oct 17, 2022 by Chris Spear

SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if you want to reuse the methods but change the type of properties? Use a parameter and specialize it!
Part 1: The Global FPGA Semiconductor Market

Resource (Verification Horizons Blog) - Oct 16, 2022 by Harry Foster

In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. The 2021 global semiconductor market was valued at $552.5 billion after experiencing a 24 percent growth over 2020. The FPGA portion of the semiconductor market was valued at about $5.3 billion in 2021. The FPGA semiconductor market is expected to reach a value of $9.3 billion by 2030, growing at a compounded annual growth rate (CAGR) of 6.5 percent during this forecast period.
UVM Testbench Debug – A Day At The Beach – Right?

Resource (Verification Horizons Blog) - Oct 04, 2022 by Rich Edelman

Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the beach. At my house, summer is definitely over but we’re still getting a declining number of “summer hot” days – without the benefit of the beach. This summer we spent some time doing nothing much at the beach. But it’s hard to shut it all down – I kept thinking about how debug is like a day at the beach…
Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

Webinar - Sep 30, 2022 by Martin Rowe

In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.
SystemVerilog: Implicit handles

Resource (Verification Horizons Blog) - Sep 06, 2022 by Chris Spear

How can your routine access a class-level variable when there is a local variable with the same name? This often happens when a set() method or the constructor initializes a class property with an argument. A common style is to give the argument the same name as the class property, such as weight shown here. If the assignment was just “weight = weight”, both names would refer to the closest definition, which is the routine argument.
SystemVerilog: Class Member Visibility

Resource (Verification Horizons Blog) - Aug 29, 2022 by Chris Spear

With most OOP languages, you are encouraged to limit direct access to class members, especially properties (variables), to prevent this sort of bug. The recommendation is to create set() and get() methods. In SystemVerilog, the default access is public, which means that other code can read and write properties and call all methods (routines). There is no keyword for this behavior.
UVM Framework Release 2022.3

Resource (Tarball) - Aug 15, 2022 by Bob Oden
Finding Data

Resource (Verification Horizons Blog) - Jul 28, 2022 by Rich Edelman

Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed). But enough with weeding. What are some debug techniques that I can use in everyday life? In this installment of using Visualizer Debug Environment – “Finding Data” will offer useful debug and visualizations for everyday debug.
How to Use Checklists for DO-254 Verification

Resource (Verification Horizons Blog) - Jul 07, 2022 by Tammy Reeve - Patmos Engineering Services

Document DO-254 provides aerospace and defense companies with the needed guidance to develop and verify airborne electronic hardware. Some clients use products like Siemens’ Questa to fulfill vital verification objectives of DO-254 such as hardware behavior simulation and code coverage as a means for elemental analysis. But did you know a simple checklist can also be an effective DO-254 verification tool?
Back to the Future with Formal Property Checking

Article - Jul 05, 2022 by Harry Foster

Back in 2010, I decided that instead of documenting a specific instance of applying formal property checking on a particular design, I would step back and look at the formal property checking process holistically. The goal was to define a set of repeatable steps that could be applied to any design. Fast forward to today, where I update the original by keeping the content that is still relevant and augmenting it with the new philosophies, methodologies, and technologies that have evolved since.
The Democratization of Digital Methodologies for AMS Verification

Article - Jul 05, 2022 by Sumit Vishwakarma

A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.
Getting to Know Visualizer - Part II

Article - Jul 05, 2022 by Rich Edelman

Welcome to part 2 of our overview of the Visualizer Debug Environment, the user interface to debug, analyze and verify all our Siemens functional verification tools. As we saw in part 1 , Visualizer is first and foremost a waveform debugger, with a host of other powerful debug capabilities also provided and supporting Verilog, SystemVerilog, VHDL, System C and C/C++. In this part of the article, we’ll look at driver tracing, X tracing, schematics, glitch debug, low power debug and more.
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces

Article - Jul 05, 2022 by Himani Kaushik - Siemens EDA

Since the advent of digitalization, there has been an exponential growth in the volume of data. With this boost in the amount of data, hard disk drives (HDDs) could not sustain the data transfer rates, leading to bottlenecks in data access. Solid state drives (SSDs) have come to the forefront as a promising solution to our modern-day storage demands. SSDs are constantly evolving with upgrades of their critical components to provide high access speeds.