Search Results
Filters
Advanced Search
2131 Results
-
MARLUG - 2024
Seminar - Sep 18, 2024 by Austin Mam
User2User Mid-Atlantic is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools.
-
Assertions and Benefits of Abstractions in Formal Verification
Resource (Verification Horizons Blog) - Sep 11, 2024 by Nicolae Tusinschi
Assertions are typically specified using languages like SystemVerilog Assertions (SVA) or Property Specification Language (PSL). These languages provide constructs for expressing complex design behaviors, making it possible to verify a wide range of conditions and scenarios.
-
Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Webinar - Sep 11, 2024 by Nicolae Tusinschi
In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge, providing user-friendly interfaces, significantly reducing verification environment setup time. Optimized for top-tier performance and scalability, Questa Formal VIP AMBA achieves high-efficiency with accurate protocol compliance.
-
Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Resource (Slides (.PDF)) - Sep 11, 2024 by Nicolae Tusinschi
Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don't miss this opportunity to learn how to streamline your verification process and enhance your design workflows.
-
Understanding Formal Verification
Resource (Verification Horizons Blog) - Sep 05, 2024 by Nicolae Tusinschi
Formal verification is a method to ensure that a hardware design behaves as intended by using mathematical analysis to check its correctness relative to its specifications. Unlike traditional verification methods, which rely on testing and simulation, formal verification mathematically proves that a design will always function correctly under all possible scenarios.
-
Jump-Start Your UVM Journey with UVM Framework (UVMF)
Resource (Verification Horizons Blog) - Sep 04, 2024 by Dennis Brophy
Bob Oden shares insights on how the Universal Verification Methodology Framework (UVMF) is revolutionizing the verification landscape. UVMF is an advanced toolset that extends the capabilities of UVM, providing a robust and structured approach to verification.
-
Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C
Paper - Aug 29, 2024 by Rich Edelman
Blending SystemVerilog UVM and SystemVerilog DPI-C is a powerful way to create or reuse pre-existing verification environments. This paper describes the mechanisms and methods and syntax needed, including writing tasks and functions in both the SystemVerilog interface and the UVM sequences.
-
Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C
Resource (Paper (.PDF)) - Aug 29, 2024 by Rich Edelman
This paper describes the mechanisms and methods and syntax needed, including writing tasks and functions in both the SystemVerilog interface and the UVM sequences.
-
Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C
Resource (Slides (.PDF)) - Aug 29, 2024 by Rich Edelman
The reader of this paper will have all the knowledge and a working example describing how to design and build a verification environment that allows for reuse of C modeling and performance tests as part of a SystemVerilog UVM testbench.
-
UVM Connect 2.3.4 Kit
Resource (Tarball) - Aug 29, 2024 by John Stickley
The uvmc-2.3.4 release adds a tew test case for 4-phase transactions using nb2b feature.
-
UVM Connect 2.3.4 Primer
Resource (Reference Documentation) - Aug 29, 2024 by John Stickley
The UVMC library is provided as a separate, optional package to UVM. You do not need to import the package if your environments do not require cross-language TLM connections or access to the UVM Command API.
-
UVM Connect 2.3.4 Release Notes
Resource (Reference Documentation) - Aug 29, 2024 by John Stickley
These notes provide information about version updates, bugfixes, known issues, changes to supported platforms, etc. Updates and changes made prior to public release are not included.
-
The Future of Multi-Die System Verification with UCIe
Resource (Slides (.PDF)) - Aug 21, 2024 by Justin Bunnell
Universal Chiplet Interconnect express (UCIe) is an open chiplet interconnect standard that enables efficient connectivity and interoperability between multiple dies on the same package. This solution offers numerous benefits including low power consumption, high bandwidth, multiple protocol support, and interoperability between chiplets of varying performance characteristics.
-
The Future of Multi-Die System Verification with UCIe
Webinar - Aug 21, 2024 by Justin Bunnell
In this session, you will be introduced to the UCIe protocol with a focus on the latest evolutions of the specification, followed by a deep dive into the key features of Siemens Avery UCIe Verification IP that enable efficient verification of multi-die systems. These include dynamic block-level and System-in-Package (SiP) level testbench creation, intelligent traffic generation, error injection, advanced debug features, and comprehensive performance monitoring.
-
Advanced Analytics for Accelerating RDC Verification Closure
Resource (Verification Horizons Blog) - Aug 13, 2024 by Reetika - Siemens EDA
Complex reset mechanisms are embedded in advanced SoCs to meet low-power and high-performance requirements. Multiple reset domains in a design can cause reset domain crossing (RDC) issues when data from one asynchronous source reset domain propagates to either a different asynchronous, synchronous, or no-reset destination domain.
-
Portable Stimulus and VIP: Like a Hand in a Glove
Resource (Verification Horizons Blog) - Aug 08, 2024 by Tom Fitzpatrick
Many of you know that I am particularly passionate about the Portable Stimulus Standard (PSS) and wanted to let you know that my recording of “Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove” is now available on Verification Academy .
-
Announcing Avery UCIe 2.0 Verification IP from Siemens EDA
Resource (Verification Horizons Blog) - Aug 06, 2024 by Gordon Allan
Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s public launch of the UCIe 2.0 specification at the Future of Memory and Storage conference event in Santa Clara, California. We are ready and open for business, and are your design verification source for all things UCIe.
-
UVM Framework Release 2023.4_2
Resource (Tarball) - Aug 05, 2024 by Bob Oden
Generator Updates: Replaced new with factory create for construction of broadcasted transaction from monitor.
-
Verification Challenges and Solutions for Multi-Die Systems (UCIe)
Resource (Verification Horizons Blog) - Jul 29, 2024 by Vivek Kaliki - Siemens EDA
Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However, these advantages come with challenges in functional verification and system analysis. To ensure thorough verification, all components in the dies must be thoroughly verified from a system-level perspective.
-
Accelerating Verification of Computational Storage Designs (NVMe)
Resource (Verification Horizons Blog) - Jul 29, 2024 by Vivek Kaliki - Siemens EDA
Computational storage is revolutionizing data storage by embedding computational capabilities within storage devices, significantly boosting system efficiency by reducing data movement. However, this innovation also complicates the design and verification processes. Ensuring the proper functioning of computational storage devices within the existing NVMe infrastructure presents significant challenges requiring advanced verification solutions.
-
Accelerate Closure of Reset Path and Reset Domain Crossing Issues in Digital Designs
Resource (Verification Horizons Blog) - Jul 24, 2024 by Farhad Ahmed
In tight project windows, engineers tend to use waiver mechanisms and/or use constraints (i.e., setting false paths) to completely eliminate paths from reset domain crossing (RDC) analysis, which can result in RDC bug escapes. In a recent DVCon conference presentation, a design engineer declared “jihad” against such use of waivers and constraints to remove certain reset paths from being properly analyzed.
-
Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim
Webinar - Jul 24, 2024 by Fan Zhang
In this session, you will be provided with an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally, we'll delve into QEMU, the open-source system emulator, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow.
-
Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim
Resource (Slides (.PDF)) - Jul 24, 2024 by Fan Zhang
In this session, we aim to provide an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally, we'll delve into QEMU, the open-source system emulator, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow.
-
Questa CDC-FX: Metastability Effects Delay Modeling
Paper - Jun 28, 2024 by Kurt Takara
In this paper, we survey traditional metastability effect models and discuss the shortcomings of each of them. We then present the model used by Questa CDC-FX, from Siemens EDA, and describe why it is a more accurate and complete metastability-effects model.
-
Questa CDC-FX: Metastability Effects Delay Modeling
Resource (Paper (.PDF)) - Jun 28, 2024 by Kurt Takara
This paper describes why metastability occurs in designs with asynchronous clocks and analyzes the various methods that designers use to verify that their design is resilient with respect to the effects of metastability. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in the Siemens EDA Questa clock-domain-crossing verification solution.