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Wednesday, Jul 22nd-8:00 AM PDT

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

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Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

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Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

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Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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Webinar (225)
Intermediate (121)
Beginner (99)
Advanced (5)

225 Results

  • UVM 1800.2 & The New and Improved UVM Cookbook

    Webinar - Sep 11, 2018 by Tom Fitzpatrick

    This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard.

  • Using Automation to Close the Loop Between Functional Requirements and Their Verification

    Webinar - Aug 10, 2018 by Brian Craw

    This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.

  • Requirement Tracing in the ISO 26262 World

    Webinar - Mar 27, 2018 by Charles Battikha

    In this session, you will learn about requirement tracing in ISO 26262 and the basics of the ISO 26262 standard as it applies to requirements for electronic design & verification of safety critical products.

  • Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs

    Webinar - Mar 07, 2018 by Ellie Burns

    In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.

  • Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?

    Webinar - Dec 12, 2017 by Neil Bulman

    This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.

  • An Introduction to DO-254 and Advanced Verification

    Webinar - Nov 02, 2017 by Tom Fitzpatrick

    DO-254 describes the objectives of a verification process to allow the development of systems that meet your design assurance goals. This web seminar will explain the critical aspects of a DO-254-compliant process and show how many advanced verification techniques and tools may be applied to satisfy these objectives.

  • Coverage & Plan-Driven Verification for FPGAs

    Webinar - Sep 06, 2017 by Brian Mathewson

    This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.

  • SystemVerilog OOP Basics used in UVM Verification

    Webinar - Jul 12, 2017 by Dave Rich

    In this session, you will learn some of the core concepts behind Object-Oriented Programming to help you get a better understand what a methodology like the UVM can do for you.

  • Breaking the Speed Limits on SoC Verification with Questa

    Webinar - May 17, 2017 by Gordon Allan

    In this session, you will learn industry best practices in verification flows and how to implement the optimal flow to speed your SoC design verification cycle.

  • Use Formal to Check Logic Faults

    Webinar - Mar 17, 2017 by Mark Eslinger

    In this session, you will learn how to use Formal to check if your RTL is sensitive to any logic faults, and how can you verify that the internal safety mechanism handles them to avoid a catastrophic failure.

  • What is CDC Protocol Verification: Why You Absolutely Need It to Prevent Bugs in Your Silicon

    Webinar - Dec 05, 2016 by Kurt Takara

    In this session, we discuss the pros and cons of various approaches to verifying Clock-Domain Crossing (CDC) protocols and we show how Questa CDC automatically generates protocol assertions.

  • How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration

    Webinar - Dec 05, 2016 by Mark Eslinger

    In this session, you will learn how to shorten your formal debug time and how using formal to explore design functionality.

  • FPGA Prototyping: Maximize Your Enterprise Debug Productivity

    Webinar - Nov 11, 2016 by Stephen Bailey

    In this session, you will learn how to maximize your enterprise debug productivity.

  • Industry Trends in Today’s Functional Verification Landscape

    Webinar - Nov 11, 2016 by Harry Foster

    In this session, you will learn more about today's industry trends in the functional verification landscape including static and dynamic verification.

  • Enterprise Verification Debug and Analysis

    Webinar - Nov 11, 2016 by Stephen Bailey

    In this session, you will learn how debug and analysis fits into a platform-based verification solution.

  • Enterprise Debug for Formal Verification

    Webinar - Nov 11, 2016 by Joe Hupcey

    In this session you learn more about formal-centric enterprise debug.

  • Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy

    Webinar - Sep 09, 2016 by Gordon Allan

    In this session we will deliver five steps your team can take to improve first pass success, and how Questa enables your advanced verification goals every step of the way.

  • Staying Competitive with FPGA Advanced Verification

    Webinar - Aug 10, 2016 by Bryan Ramirez

    In this session you will learn about trends in the FPGA industry that are pushing the need for advanced verification.

  • UVM Framework: Create a UVM Environment in Less than an Hour

    Webinar - Nov 25, 2015 by Bob Oden

    In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.

  • Leveraging Verification IP (VIP) for Fast & Efficient Verification

    Webinar - Nov 25, 2015 by Jason Polychronopoulos

    In this session you will learn how Verification IP (VIP) helps to overcome IP verification challenges.

  • New Low Power Verification Techniques

    Webinar - Sep 23, 2015 by Ellie Burns

    This session highlights a "new school" low power methodology termed "successive refinement" that uses the strength of UPF in just such a structured approach.

  • New School Thinking for Fast and Efficient Verification Using EZ-VIP

    Webinar - Sep 02, 2015 by Jason Polychronopoulos

    The session will show how to swiftly move through VIP instantiation, connection, configuration and protocol initialization, covering the use of UVM based verification IP for protocols such as PCI Express and MIPI CSI and DSI.

  • New School Regression Control

    Webinar - Sep 01, 2015 by Darron May

    Getting the very best from your verification resources requires a regression system that understands the verification process and is tightly integrated with workload management and distributed resource management software. Both requirements depend on visibility into available software and hardware resources, and by combining their strengths, users can massively improve productivity by reducing unnecessary verification cycles.

  • Evolution of Debug

    Webinar - Aug 25, 2015 by Gordon Allan

    In this session, Gordon Allan takes a critical look at the past, present and future challenges for debug, exploring real world situations drawn from years of experience in SoC design and verification, and describing leading-edge techniques and compelling solutions.

  • New School Connectivity Checking

    Webinar - Jul 01, 2015 by Mark Eslinger

    This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.