- Awashesh Kumar - Mentor, A Siemens Business
- Madhur Bhargava - Mentor, A Siemens Business
- Vinay Singh - Mentor, A Siemens Business
- Pankaj Gairola- Mentor, A Siemens Business
The effective verification of low-power designs has been a challenge for many years now. The IEEE Std 1801™-2015 Unified Power Format (UPF) standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs. One of the main challenges for low-power verification engineers has been the fact that there is a disconnect between the traditional RTL and low-power objects. Users cannot access and manipulate the low-power objects in the same way as they do for RTL. Low-power concepts are abstract and complexities arise because of the number of sources like UPF, HDL and Liberty all provide power intent in a low-power design. It has also been seen that the majority of verification time is spent debugging complex low-power issues. There are not too many ways in which users can do self-checking of their designs. As the low-power architecture is complex and the number of power-domains used in the design is high, selective reporting of a part of design is needed The lack of an industry standard in this regard resulted in inconsistency in the different ad-hoc approaches adopted by different tool vendors.
To keep pace with the increasing complexity of low-power architectures the IEEE 1801 standard is expanding its gamut of constructs and commands to include more scenarios of low-power verification and implementation. In this paper, we will discuss how the UPF 3.0 information model HDL package functions and Tcl query functions can be used to do innovative things, which are often a very important low-power design verification criteria. In this paper we will present some innovative ways of writing PA apps using the UPF 3.0 information model HDL package functions and Tcl query functions. The paper also demonstrates how these low-power applications (aka PA apps) can help in reporting, debugging and self-checking of low-power designs. We will also highlight how these apps will help offer an efficient way to significantly save verification effort and time.
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Read the entire Low Power Apps: Shaping the Future of Low Power Verification technical paper.