Verification Academy

Topic	Replies	Views	Activity
ReadmemH from one source file to cascaded mem RTL SystemVerilog	1	83	July 2, 2024
Free tool to use concurrent assertions SystemVerilog	1	111	June 14, 2024
Book/manual for code coverage Coverage	0	57	February 6, 2025
Desired value of a register doesn't get updated UVM	0	42	December 17, 2024
Sample coverage after check Coverage	0	75	October 23, 2024
Latch causing simulation perf issues SystemVerilog always_latch	2	37	March 30, 2025
Signal value is not same on terminal with waveform SystemVerilog	2	59	September 24, 2024
Using "time" as the unit of a parameter SystemVerilog	2	199	September 9, 2024
UVM RAL writes, reads and prediction UVM UVM , RAL	0	56	February 11, 2025
How to Wrap UVM Environment and Test for Reuse as VIP? UVM	0	52	January 27, 2025
Pure-Virtual functions (create and get_type_name) in uvm_object UVM	0	92	August 2, 2024
PCIe Question about LCRC and ECRC! SystemVerilog SystemVerilog , UVM , PCIe , PCIe-Gen-5 , pcie-protocol-explanation	1	36	May 30, 2025
Transaction recording outside of a sequence UVM	1	32	May 15, 2025
Uvm_reg_predictor for volatile register modelling UVM	1	32	May 9, 2025
Finish_item argument in sequence body method UVM	1	47	April 22, 2025
String conversion to real SystemVerilog	1	31	April 17, 2025
How to retrieve the correct values of continuously driven values of DUT in the test bench SystemVerilog	1	46	March 27, 2025
Super.new()in derived class behavior SystemVerilog supernew	1	30	March 8, 2025
Fork/join_none at funciton/task call or definition SystemVerilog	1	56	February 13, 2025
Verification Horizons pre 2013 Downloads Verification-Horizons	1	46	January 28, 2025
$cast failed when casting sequence item SystemVerilog cast	1	80	October 10, 2024
Can a class have a data member that is a pointer/ref to a logic? SystemVerilog	1	124	September 7, 2024
Suggestions for uvm_phase API UVM UVM , UVM_PHASE	1	97	July 25, 2024
Doubts about recursion in Verilog and systemverilog static world SystemVerilog	1	161	June 23, 2024
Loop through nested struct in SV SystemVerilog structure-and-union , loop	2	100	October 1, 2024
Grammar does not support let expressions with select – bug or feature? SystemVerilog	2	105	August 29, 2024
Scoreboard logic for a router. [Interview Question] UVM UVM-scoreboard	0	50	May 28, 2025
Constraining Credits SystemVerilog SystemVerilog , randomization	0	104	September 7, 2024
What is an interface? not in code but inside a chip what is it actually? what does it contain? Im confusing it with protocol SystemVerilog	1	29	May 21, 2025
SEQREQZMB Error on shut down pahse UVM	1	25	May 15, 2025
Time statement is incomplete SystemVerilog	1	29	May 7, 2025
Constraint failure on different variables other than variables used in Inline constraint SystemVerilog constraint-randomization , randomization	1	31	April 30, 2025
Task with clock-triggered behavior causes unexpected signal update timing SystemVerilog SystemVerilog	1	31	April 18, 2025
SystemVerilog generate label as signal name SystemVerilog SystemVerilog , generate , generate-block	1	57	March 28, 2025
Can Overriden method declared as local in child class ,be accessed in other scope? SystemVerilog	1	31	February 25, 2025
#1step in clocking block for input and output SystemVerilog SystemVerilog	1	81	December 3, 2024
I encounter UVM_WARININGs for race condition while doing register set/writes UVM UVM	1	95	September 5, 2024
Sscanf usage to read lines from file SystemVerilog	1	114	September 3, 2024
Access VHDL hierarchical objects from a SV testbench SystemVerilog VHDL	1	107	June 26, 2024
Working of strong operator & final block SystemVerilog SystemVerilog , SVA	0	40	April 29, 2025
Randomly Divide Fixed Memory into Non-Overlapping Blocks SystemVerilog	0	48	March 10, 2025
Implementing Block-Level Testbench with Valid-Ready Protocol annd req and resp UVM	0	59	January 27, 2025
Bind to a module which is uninstantiated but bounded to another module SystemVerilog bind	3	36	October 23, 2024
Accessing complex hierarchy through bind statement SystemVerilog	2	61	October 22, 2024
UVM RAL: Mapping Same Register Block to Two Address Ranges UVM RAL , uvm-ral	0	33	March 12, 2025
Query regarding witness for vacuosly passing assertions in Formal Verification SystemVerilog assertion , SVA	1	27	June 12, 2025
How to downcast if the derived object type is not known UVM	1	42	April 12, 2025
Does +uvm_set_config_* plusargs only work for uvm_components and not for uvm_objects UVM UVM	1	32	March 10, 2025
Using uvm_printer in a uvm_component class to print certain variables only UVM uvm_printer	1	33	February 14, 2025
Issue with modulation in ASIC porject WiMax SystemVerilog	1	21	January 4, 2025