Super.new()in derived class behavior

SystemVerilog
1

I’m trying to understand super.new() behavior when its called in the derived class… I was expecting the super.new(value) call in the child class to assign 77 to its variable “value” . Or if it got assigned to base class’s value wouldn’t that still be available to the child class because of inheritence

class BaseClass;   
  int value;  
  function new (int value);
    $display("function new from BaseClass"); 
    this.value = value;  
  endfunction 
  
  function void display();
    $display("display function from BaseClass = %d", value); 
  endfunction 
endclass 

class SubClass extends BaseClass; 
int value; 
function new (int value);
super.new(value);
//this.value = value; 
endfunction 
  
function void display();
$display("display function from ChildClass = %d", value); 
endfunction   
endclass



module tb; 
BaseClass bc; 
SubClass sc; 
initial begin
  bc = new (44);
  sc = new (77); 
  
  bc.display(); 
  sc.display(); 
end
endmodule

Results:
function new from BaseClass
function new from BaseClass
display function from BaseClass = 44
display function from ChildClass = 0 → Why is this 0 instead of 77?

2

You’ve made this overly complicated because you’ve declared four variables with the same name–value.

  • BaseClass::value
  • BaseClass::new() value
  • SubClass::value
  • Subclass::new() value

You commented out the assignment to SubClass::value

By declaring SubClass::value, you have hidden BaseClass::value from SubClass::display(). You can still access it explicitly with BaseClass::value. In general, it’s a very bad programming practice to declare class members with the same name in an extended class that exists in its base class.