Bind to a module which is uninstantiated but bounded to another module

SystemVerilog
1

I have a checker file that is bound to the design instance.
bind dut dut_checker(.*);

I have separated some of the coverage-related code inside the checker and put it in a new module dut_coverage.

I did it with the impression that I would be able to bind it to dut_checker like below -
bind dut_checker dut_coverage (.*);

I hit an error because there is no direct instantiation of dut_checker.

Any workaround for this problem?

PS: The coverage file references multiple internal variables of dut_checker, making it impossible to bind to the RTL instance.

2

The LRM section 23.11 Binding auxiliary code to scopes or instances explicitly says:

It shall be an error for a bind statement to bind a bind_instantiation underneath the scope of another bind_instantiation.

You should instantiate the dut_coverage module directly inside the dut_checker module. The bind construct is a construct that allows you to instantiate verification code into your RTL without having to modify the original RTL code.

3

Thanks, Dave!

Can the variables of the dut_checker module be accessed using the relative hierarchical reference in dut_coverage if it is instantiated in dut_checker?

Say I have a coverpoint for a variable xyz of the checker.
Is dut_checker.xyz valid in dut_coverage module or should the hierarchy start from the top i.e. top.dut_checker_inst.xyz??

// Pseudocode

module dut_checker();
bit xyz;
....
// Instantiated the coverage below
dut_coverage dut_coverage_inst();

endmodule

module dut_coverage();
...
coverpoint dut_checker.xyz;
...
endmodule
4

Yes. 23.8 Upwards name referencing