Constraint failure on different variables other than variables used in Inline constraint

SystemVerilog
,
1

I am trying to re-randomize a variable "c’ in an object “item” using inline constraint inside a test class. The randomization of the whole object “item” is happening in the base class "example_base_test " and re-randomization is happening in the extended test “test_1”. The issue i am facing is that, after the inline constraint is applied, the constraint solver fails to solve c1 inside object “item”.

Kindly find code snippet below.

Thanks in advance.

class item extends uvm_object;
rand bit a, b ;
rand int c;

constraint c1{
	if (a)        b ==0;
}
endclass


class test_1 extends example_base_test  ;
	`uvm_component_utils(test_1)

	// The test’s constructor
	function new (string name = "test_1",uvm_component parent = null);
		super.new(name, parent);
	endfunction
		
	virtual function build_phase(); 
		super.build_phase(phase);
		if(!item.randomize(c) with {
                        c > 30;
						c < 150;
        })begin 
			`uvm_error(get_type_name(), "randomization failed ");
       end 
	   uvm_config_db#(item)::set(this, "*", "item", item);
	endfunction
endclass
3

You’ve made some typos. item can’t be both a type and a variable name. I’m assuming you meant req in some places.

A note about using req.randomize(c) .... This means that only variable c is kept as a random variable, and a,b become state variables. However, all active constraints remain. An in-line constraint gets added to the built-in randomize method.

I think you want to use std:: randomize. Then only the in-line constraint is applied.

	if(!std::randomize(req.c) with {
                        req.c > 30;
						req.c < 150;

See section 18.12 Randomization of scope variables—std::randomize() in the IEEE 1800-2023 SystemVerilog LRM.

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