SystemVerilog generate label as signal name

SystemVerilog
, ,
1

Dear Forum,

I saw this syntax in some open source coding :

    generate
       for (i=0;i<`N ;i=i+1) begin:gen_label
          wire p ;
	      ...
       end
    endgenerate
    assign sig = gen_label[0].p; // use of 'gen_label' as signal here

I am wondering if this is correct and what it means exactly ?

Many Thanks
Jamal

2

A named begin/end block creates a hierarchical scope. In the case of a generated for-loop an iteration index gets appended to the scope name.

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