Hello people,
I am Sai Kumar, and I am working on a project of FIFO to learn about the System Verilog test bench flow. I need to get the values of two signals which are empty and full which are driven continuously in the DUT how to calculate their exact values at the moment of those Values in the reference model.
What are the steps I need to follow in the test bench since i cannot use assign statement in my Reference model, since it is a class.
I hope you understand my query and reply to me with the suitable suggestion
Thank you