Latch causing simulation perf issues

SystemVerilog
1

We have recently added the following module that contains a latch to our design repo. The module is instanced 3000+ times in our design, and has caused a major simulation performance degradation. Here is the source code:

module clk_gater (
  input  clk,
  input  clk_en,
  input  TE,
  output clk_gated
);
  
  reg clk_en_latch;
  
  always_latch begin
    if (~clk) begin
      clk_en_latch = (clk_en | TE);
    end
  end

We use VCS as our simulator, and its simulation profiler is telling us that the latch in this module is accounting for 13% of our simulation wallclock time. Our design is huge, so it’s laughable to think that a latch is causing such a problem - even if it’s instanced this many times.

I’m a DV engineer, not an RTLer, so I don’t implement latches ever. Two things that look fishy to me are:

  1. The use of a clock signal as the input expression to an if statement.
  2. The signal “clk_en_latch” is a variable, and not a wire.

Anyone have any recommendations for how to improve the simulation performance of the code above?

2

This might be a tool specific issue, but even if not, debugging it would be a tool specific feature.

This Siemens sponsored public forum is not for discussing tool specific issues. Please read your tool’s User Manual or contact your tool vendor for support.

3

Thanks @dave_59. What I was hoping to gain from this forum is feedback about the implementation of the latch itself. Whether folks see anything in the coding that would lead to simulator-agnostic performance issues. It seems to me that the current implementation is going to cause the output of the latch to be re-evaluated on every clk edge. For simulation performance purposes, I’d only want the latch output to be evaluated when clk_en or TE change.